| Message ID | 1604511926-29516-1-git-send-email-claudiu.beznea@microchip.com |
|---|---|
| Headers | show |
| Series | clk: at91: adapt for dvfs | expand |
On 11/4/20 7:45 PM, Claudiu Beznea wrote: > pmc_data_allocate() has been changed. pmc_data_free() was removed. > Adapt the code taking this into consideration. With this the programmable > clocks were also saved in sama7g5_pmc so that they could be later > referenced. > > Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5") > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com> > --- > drivers/clk/at91/sama7g5.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c > index 0db2ab3eca14..a092a940baa4 100644 > --- a/drivers/clk/at91/sama7g5.c > +++ b/drivers/clk/at91/sama7g5.c > @@ -838,7 +838,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) > sama7g5_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1, > nck(sama7g5_systemck), > nck(sama7g5_periphck), > - nck(sama7g5_gck)); > + nck(sama7g5_gck), 8); > if (!sama7g5_pmc) > return; > > @@ -980,6 +980,8 @@ static void __init sama7g5_pmc_setup(struct device_node *np) > sama7g5_prog_mux_table); > if (IS_ERR(hw)) > goto err_free; > + > + sama7g5_pmc->pchws[i] = hw; > } > > for (i = 0; i < ARRAY_SIZE(sama7g5_systemck); i++) { > @@ -1052,7 +1054,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) > kfree(alloc_mem); > } > > - pmc_data_free(sama7g5_pmc); > + kfree(sama7g5_pmc); > } > > /* Some clks are used for a clocksource */ >
Hi, Please ignore this series for the moment as I will have to run few more tests on it. Sorry for the noise! Thank you, Claudiu Beznea On 04.11.2020 19:45, Claudiu Beznea wrote: > Hi, > > SAMA7G5 is capable of DVFS. The supported CPU clock frequencies could be > obtained from CPU PLL. The hardware block diagram for clock feeding the > CPU is as follows: > > +--------+ > +-->|divider1|--> CPU clock > | +--------+ > +--------+ +----------+ | +--------+ > |CPU PLL |-->|prescaller|--+-->|divider0|--> MCK0 clock > +--------+ +----------+ +--------+ > > When switching CPU clock frequencies the MCK0 is also changed by DVFS > driver to avoid its over/under clocking (depending on CPU clock frequency > requested by DVFS algorithms). Some of IPs feed by MCK0 are MCK0 glich > aware, some are not. For this MCK0 was removed from the parents list of > the IPs which are not MCK0 glitch aware (patch 5/8). > > This series adapt AT91 clocks (mostly sam9x60-pll and master clock drivers) > so that runtime changes of these clocks to be allowed. > > The CPU clock was registered from prescaller clock (see above diagram) > and no software control has been added for divider1 because the frequencies > supported by SAMA7G5's CPU could be directly obtained from CPU PLL + > prescaller. > > On top of this series I also added a fix for sama7g5.c code (patch 1/8). > Please let me know if you would like me to send this one separtely (it > would be nice if this fix could be integrated in 5.10). > > Thank you, > Claudiu Beznea > > Changes in v2: > - s/at91rm9200_mck_lock/at91sam9260_mck_lock in patch 7/8 > > Claudiu Beznea (6): > clk: at91: sama7g5: fix compilation error > clk: at91: clk-sam9x60-pll: allow runtime changes for pll > clk: at91: sama7g5: remove mck0 from parent list of other clocks > clk: at91: sama7g5: decrease lower limit for MCK0 rate > clk: at91: clk-master: re-factor master clock > clk: at91: sama7g5: register cpu clock > > Eugen Hristev (2): > dt-bindings: clock: at91: add sama7g5 pll defines > clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and > referenced in DT > > drivers/clk/at91/at91rm9200.c | 20 ++- > drivers/clk/at91/at91sam9260.c | 24 ++- > drivers/clk/at91/at91sam9g45.c | 30 ++-- > drivers/clk/at91/at91sam9n12.c | 34 ++-- > drivers/clk/at91/at91sam9rl.c | 22 ++- > drivers/clk/at91/at91sam9x5.c | 27 +++- > drivers/clk/at91/clk-master.c | 323 +++++++++++++++++++++++++++++++------ > drivers/clk/at91/clk-sam9x60-pll.c | 102 ++++++++++-- > drivers/clk/at91/dt-compat.c | 15 +- > drivers/clk/at91/pmc.h | 20 ++- > drivers/clk/at91/sam9x60.c | 35 ++-- > drivers/clk/at91/sama5d2.c | 41 +++-- > drivers/clk/at91/sama5d3.c | 37 +++-- > drivers/clk/at91/sama5d4.c | 39 +++-- > drivers/clk/at91/sama7g5.c | 139 +++++++++------- > include/dt-bindings/clock/at91.h | 11 ++ > 16 files changed, 692 insertions(+), 227 deletions(-) >
Hi, SAMA7G5 is capable of DVFS. The supported CPU clock frequencies could be obtained from CPU PLL. The hardware block diagram for clock feeding the CPU is as follows: +--------+ +-->|divider1|--> CPU clock | +--------+ +--------+ +----------+ | +--------+ |CPU PLL |-->|prescaller|--+-->|divider0|--> MCK0 clock +--------+ +----------+ +--------+ When switching CPU clock frequencies the MCK0 is also changed by DVFS driver to avoid its over/under clocking (depending on CPU clock frequency requested by DVFS algorithms). Some of IPs feed by MCK0 are MCK0 glich aware, some are not. For this MCK0 was removed from the parents list of the IPs which are not MCK0 glitch aware (patch 5/8). This series adapt AT91 clocks (mostly sam9x60-pll and master clock drivers) so that runtime changes of these clocks to be allowed. The CPU clock was registered from prescaller clock (see above diagram) and no software control has been added for divider1 because the frequencies supported by SAMA7G5's CPU could be directly obtained from CPU PLL + prescaller. On top of this series I also added a fix for sama7g5.c code (patch 1/8). Please let me know if you would like me to send this one separtely (it would be nice if this fix could be integrated in 5.10). Thank you, Claudiu Beznea Changes in v2: - s/at91rm9200_mck_lock/at91sam9260_mck_lock in patch 7/8 Claudiu Beznea (6): clk: at91: sama7g5: fix compilation error clk: at91: clk-sam9x60-pll: allow runtime changes for pll clk: at91: sama7g5: remove mck0 from parent list of other clocks clk: at91: sama7g5: decrease lower limit for MCK0 rate clk: at91: clk-master: re-factor master clock clk: at91: sama7g5: register cpu clock Eugen Hristev (2): dt-bindings: clock: at91: add sama7g5 pll defines clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT drivers/clk/at91/at91rm9200.c | 20 ++- drivers/clk/at91/at91sam9260.c | 24 ++- drivers/clk/at91/at91sam9g45.c | 30 ++-- drivers/clk/at91/at91sam9n12.c | 34 ++-- drivers/clk/at91/at91sam9rl.c | 22 ++- drivers/clk/at91/at91sam9x5.c | 27 +++- drivers/clk/at91/clk-master.c | 323 +++++++++++++++++++++++++++++++------ drivers/clk/at91/clk-sam9x60-pll.c | 102 ++++++++++-- drivers/clk/at91/dt-compat.c | 15 +- drivers/clk/at91/pmc.h | 20 ++- drivers/clk/at91/sam9x60.c | 35 ++-- drivers/clk/at91/sama5d2.c | 41 +++-- drivers/clk/at91/sama5d3.c | 37 +++-- drivers/clk/at91/sama5d4.c | 39 +++-- drivers/clk/at91/sama7g5.c | 139 +++++++++------- include/dt-bindings/clock/at91.h | 11 ++ 16 files changed, 692 insertions(+), 227 deletions(-)