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[v3,00/15] drm/mediatek: add support for mediatek SOC MT8192

Message ID 1610351031-21133-1-git-send-email-yongqiang.niu@mediatek.com
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Series drm/mediatek: add support for mediatek SOC MT8192 | expand

Message

Yongqiang Niu Jan. 11, 2021, 7:43 a.m. UTC 
This series are based on 5.11-rc1 and SoC MT8183,
and provide 15 patch to support mediatek SOC MT8192

Changes since v2:
- fix review comment in v2
- add pm runtime for gamma and color 
- move ddp path select patch to mmsys series
- remove some useless patch

Yongqiang Niu (15):
  dt-bindings: mediatek: add description for postmask
  dt-bindings: mediatek: add description for mt8192 display
  arm64: dts: mt8192: add display node
  drm/mediatek: add component OVL_2L2
  drm/mediatek: add component POSTMASK
  drm/mediatek: add component RDMA4
  drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
  drm/mediatek: check if fb is null
  drm/mediatek: Add pm runtime support for gamma
  drm/mediatek: Add pm runtime support for color
  drm/mediatek: fix aal size config
  drm/mediatek: separate ccorr module
  drm/mediatek: add matrix bits private data for ccorr
  drm/mediatek: add DDP support for MT8192
  drm/mediatek: add support for mediatek SOC MT8192

 .../bindings/display/mediatek/mediatek,disp.txt    |   3 +-
 arch/arm64/boot/dts/mediatek/mt8192.dtsi           | 134 +++++++++++
 drivers/gpu/drm/mediatek/Makefile                  |   4 +-
 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c          | 245 +++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_color.c          |   5 +
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c          |   5 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c            |  34 ++-
 drivers/gpu/drm/mediatek/mtk_disp_postmask.c       | 161 ++++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c           |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c             |  35 +++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c        |  98 +--------
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h        |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c             |  52 ++++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h             |   2 +
 14 files changed, 687 insertions(+), 98 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c

Comments

Chun-Kuang Hu Jan. 11, 2021, 11:30 p.m. UTC | #1 
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月11日 週一 下午3:44寫道：
>
> add description for postmask
> postmask is used control round corner for display frame

After changing to 'used to control',

Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index c562cda..9d9ab65 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -37,6 +37,7 @@ Required properties (all function blocks):
>         "mediatek,<chip>-disp-aal"              - adaptive ambient light controller
>         "mediatek,<chip>-disp-gamma"            - gamma correction
>         "mediatek,<chip>-disp-merge"            - merge streams from two RDMA sources
> +       "mediatek,<chip>-disp-postmask"         - control round corner for display frame
>         "mediatek,<chip>-disp-split"            - split stream to two encoders
>         "mediatek,<chip>-disp-ufoe"             - data compression engine
>         "mediatek,<chip>-dsi"                   - DSI controller, see mediatek,dsi.txt
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Chun-Kuang Hu Jan. 11, 2021, 11:41 p.m. UTC | #2 
Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月11日 週一 下午3:48寫道：
>
> add display node
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 +++++++++++++++++++++++++++++++
>  1 file changed, 134 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index e12e024..dcf9fdf 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -15,6 +15,11 @@
>         #address-cells = <2>;
>         #size-cells = <2>;
>
> +       aliases {
> +               ovl2-2l2 = &ovl_2l2;
> +               rdma4 = &rdma4;
> +       };
> +
>         clk26m: oscillator0 {
>                 compatible = "fixed-clock";
>                 #clock-cells = <0>;
> @@ -508,5 +513,134 @@
>                         #size-cells = <0>;
>                         status = "disabled";
>                 };
> +
> +               mmsys: syscon@14000000 {
> +                       compatible = "mediatek,mt8192-mmsys", "syscon";
> +                       reg = <0 0x14000000 0 0x1000>;
> +                       //mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> +                       //       <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> +                       //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> +                       #clock-cells = <1>;
> +               };
> +
> +                mutex: mutex@14001000 {
> +                       compatible = "mediatek,mt8192-disp-mutex";
> +                       reg = <0 0x14001000 0 0x1000>;
> +                       interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       //clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> +                       //mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> +                       //                    <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
> +               };
> +
> +               ovl0: ovl@14005000 {
> +                       compatible = "mediatek,mt8192-disp-ovl";
> +                       reg = <0 0x14005000 0 0x1000>;
> +                       interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       //clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +                       //iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>;
> +                       //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;

I think you should not mark these property.

Regards,
Chun-Kuang.

> +                       //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> +               };
> +
> +               ovl_2l0: ovl@14006000 {
> +                       compatible = "mediatek,mt8192-disp-ovl-2l";
> +                       reg = <0 0x14006000 0 0x1000>;
> +                       interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +                       //clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +                       //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>;
> +                       //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> +               };
> +
> +               rdma0: rdma@14007000 {
> +                       compatible = "mediatek,mt8192-disp-rdma";
> +                       reg = <0 0x14007000 0 0x1000>;
> +                       interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       //clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> +                       //iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> +                       //mediatek,larb = <&larb0>;
> +                       //mediatek,rdma-fifo-size = <5120>;
> +                       //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +                       //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
> +               };
> +
> +               color0: color@14009000 {
> +                       compatible = "mediatek,mt8192-disp-color",
> +                                    "mediatek,mt8173-disp-color";
> +                       reg = <0 0x14009000 0 0x1000>;
> +                       interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +                       //clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +                       //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> +               };
> +
> +               ccorr0: ccorr@1400a000 {
> +                       compatible = "mediatek,mt8192-disp-ccorr";
> +                       reg = <0 0x1400a000 0 0x1000>;
> +                       interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +                       //clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +                       //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> +               };
> +
> +               aal0: aal@1400b000 {
> +                       compatible = "mediatek,mt8192-disp-aal";
> +                       reg = <0 0x1400b000 0 0x1000>;
> +                       interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +                       //clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +                       //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> +               };
> +
> +               gamma0: gamma@1400c000 {
> +                       compatible = "mediatek,mt8183-disp-gamma",
> +                                    "mediatek,mt8192-disp-gamma";
> +                       reg = <0 0x1400c000 0 0x1000>;
> +                       interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +                       //clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +                       //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> +               };
> +
> +               postmask0: postmask@1400d000 {
> +                       compatible = "mediatek,mt8192-disp-postmask";
> +                       reg = <0 0x1400d000 0 0x1000>;
> +                       interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +                       //clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> +                       //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> +               };
> +
> +               dither0: dither@1400e000 {
> +                       compatible = "mediatek,mt8192-disp-dither",
> +                                    "mediatek,mt8183-disp-dither";
> +                       reg = <0 0x1400e000 0 0x1000>;
> +                       interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +                       //clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +                       //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> +               };
> +
> +               ovl_2l2: ovl@14014000 {
> +                       compatible = "mediatek,mt8192-disp-ovl-2l";
> +                       reg = <0 0x14014000 0 0x1000>;
> +                       interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +                       //clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> +                       //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> +                       //       <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> +                       //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> +               };
> +
> +               rdma4: rdma@14015000 {
> +                       compatible = "mediatek,mt8192-disp-rdma";
> +                       reg = <0 0x14015000 0 0x1000>;
> +                       interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +                       //clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> +                       //iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> +                       //mediatek,rdma-fifo-size = <2048>;
> +                       //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> +               };
>         };
>  };
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Chun-Kuang Hu Jan. 11, 2021, 11:45 p.m. UTC | #3 
Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月11日 週一 下午3:44寫道：
>
> This patch add component OVL_2L2

Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 81ed076..a715127 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -383,6 +383,7 @@ struct mtk_ddp_comp_match {
>         [DDP_COMPONENT_OVL1]    = { MTK_DISP_OVL,       1, NULL },
>         [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,    0, NULL },
>         [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,    1, NULL },
> +       [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L,    2, NULL },
>         [DDP_COMPONENT_PWM0]    = { MTK_DISP_PWM,       0, NULL },
>         [DDP_COMPONENT_PWM1]    = { MTK_DISP_PWM,       1, NULL },
>         [DDP_COMPONENT_PWM2]    = { MTK_DISP_PWM,       2, NULL },
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Chun-Kuang Hu Jan. 12, 2021, 12:20 a.m. UTC | #4 
Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月11日 週一 下午3:48寫道：
>
> It's possible that state->base.fb is null. Add a check before access its
> format.

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang.

>
> Fixes: b6b1bb980ec4 ( drm/mediatek: Turn off Alpha bit when plane format has no alpha)
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 4934bee..8e7f494 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -279,7 +279,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
>         }
>
>         con = ovl_fmt_convert(ovl, fmt);
> -       if (state->base.fb->format->has_alpha)
> +       if (state->base.fb && state->base.fb->format->has_alpha)
>                 con |= OVL_CON_AEN | OVL_CON_ALPHA;
>
>         if (pending->rotation & DRM_MODE_REFLECT_Y) {
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Chun-Kuang Hu Jan. 12, 2021, 11:09 p.m. UTC | #5 
Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月11日 週一 下午3:48寫道：

>
> gamma power domain need controled in the device.

In this series, why only gamma and color add pm runtime support? I
think all ddp component need pm runtime support. And pm runtime
support is not related to mt8192, so move these patches out of this
series.

Regards,
Chun-Kuang.

>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> index 3c1ea07..da93079 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> @@ -10,6 +10,7 @@
>  #include <linux/of_device.h>
>  #include <linux/of_irq.h>
>  #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
>  #include <linux/soc/mediatek/mtk-cmdq.h>
>
>  #include "mtk_drm_crtc.h"
> @@ -156,6 +157,8 @@ static int mtk_disp_gamma_probe(struct platform_device *pdev)
>
>         platform_set_drvdata(pdev, priv);
>
> +       pm_runtime_enable(dev);
> +
>         ret = component_add(dev, &mtk_disp_gamma_component_ops);
>         if (ret)
>                 dev_err(dev, "Failed to add component: %d\n", ret);
> @@ -165,6 +168,8 @@ static int mtk_disp_gamma_probe(struct platform_device *pdev)
>
>  static int mtk_disp_gamma_remove(struct platform_device *pdev)
>  {
> +       pm_runtime_disable(&pdev->dev);
> +
>         component_del(&pdev->dev, &mtk_disp_gamma_component_ops);
>
>         return 0;
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Rob Herring (Arm) Jan. 14, 2021, 7:11 p.m. UTC | #6 
On Mon, 11 Jan 2021 15:43:37 +0800, Yongqiang Niu wrote:
> add description for postmask
> postmask is used control round corner for display frame
> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>
Chun-Kuang Hu Jan. 14, 2021, 10:29 p.m. UTC | #7 
Rob Herring <robh@kernel.org> 於 2021年1月15日 週五 上午3:11寫道：
>
> On Mon, 11 Jan 2021 15:43:37 +0800, Yongqiang Niu wrote:
> > add description for postmask
> > postmask is used control round corner for display frame
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> >  Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
> >  1 file changed, 1 insertion(+)
> >
>
> Acked-by: Rob Herring <robh@kernel.org>

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang.

> _______________________________________________
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> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
Chun-Kuang Hu Jan. 14, 2021, 10:55 p.m. UTC | #8 
Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年1月11日 週一 下午3:48寫道：
>
> the orginal setting is not correct, fix it follow hardware data sheet.
> if keep this error setting, mt8173/mt8183 display ok
> but mt8192 display abnormal.
>

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang.

> Fixes: 0664d1392c26 (drm/mediatek: Add AAL engine basic function)
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index fc01fea..6081800 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -174,7 +174,7 @@ static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
>                            unsigned int h, unsigned int vrefresh,
>                            unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
>  {
> -       mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
> +       mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_SIZE);
>  }
>
>  static void mtk_aal_start(struct mtk_ddp_comp *comp)
> --
> 1.8.1.1.dirty
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