From patchwork Wed Sep 30 03:16:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313820 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679539ilg; Tue, 29 Sep 2020 20:18:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxcdzK8Uz7p3HGyV3GWr3VdD7Sxg0zt2fNu6yTgTIiVh1Jdxeedvy8gU6rcYvOGYNqOOukD X-Received: by 2002:aa7:c3c8:: with SMTP id l8mr584975edr.368.1601435925512; Tue, 29 Sep 2020 20:18:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435925; cv=none; d=google.com; s=arc-20160816; b=MfJRiQyOl3l7zZGPpsWy799n30zqsS5Lao/JfBIkwNyeQcMJ7h8DRj2e0VDOt05oOm h4oYK8vl3f7FGYc5/PpdT0BGXWHL6p2HxOmlQ1GRL9dj+4phA0lIWdqWrit9c08DAiYz eNwQwyQyOmN2TAm1AAZFcKEsOPkJd6KOaTWVvhmsCMDBAlwZUithVt5osw4TqV9Z6CMH /g8/Ku1fvr3tzRb7rkxChA4jfhVFgUIGSGJbjreX6eDSfevrSL2LUXjK630xxAvD8fFp BsFF+yTgvNqXnz6//flWnkXjncdDNmA6dAt2k+CbytSYByKz/vkRbTmvkeWzKRQgq+3z baGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=lx2bsB7Oh4d6ONUDK642a7Eg1qoKAx499ef/i69vFh4=; b=F8SqTqMozXgY7Y0XmQ0284aNn5HrJHXpBx12WeZFaQT+bjRrd9PRuZhS/eO/QiJJjm 12e17Gks8+LTMcFA9sF+c2TodlYq1Xyhg2QRbCCfQsthQfAF2X6gW57wEpTP78yWDoNG I0oX4b+Q+2Le1q1YBcBR8Juz2dvyF+CHhfkNywX0gIPtdB6/fqvIHMI5KSyqO/qVdJsG yZdBbF+cM/9rhxWaS2HCSH+CnjN0M8qcMZBxxCyZEXmXiC6zktQmVoxk4Etf9WSTM5Kl gw8dcDAZhySoMLb48LCvENMZsNLFGTiYRcIGzWuQgGyprZ57pmAgqCIaieJtr091T8is wzcA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dk26si176817edb.60.2020.09.29.20.18.45; Tue, 29 Sep 2020 20:18:45 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729774AbgI3DSk (ORCPT + 6 others); Tue, 29 Sep 2020 23:18:40 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14735 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729784AbgI3DSk (ORCPT ); Tue, 29 Sep 2020 23:18:40 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 6F123A76FA735C0EF8B9; Wed, 30 Sep 2020 11:18:37 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:28 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 00/17] add support for Hisilicon SD5203 SoC Date: Wed, 30 Sep 2020 11:16:55 +0800 Message-ID: <20200930031712.2365-1-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org v5 --> v6: 1. Add a new property "#reset-cells" and update the example in Patch 15. All other patches are not changed. v4 --> v5: 1. Drop the descriptions of the common properties, such as "reg". 2. Add "additionalProperties: false" or "additionalProperties: type: object" for each new yaml file. 3. Group three Hi6220 domain controller into one yaml file, see Patch 15 4. Remove the prefix "hisilicon," of each yaml file, all of them are under hisilicon directory, no need to duplicated it. 5. move four controllers into syscon.yaml, because they have no specific properties, see Patch 1-2. 6. Add the name of the board which based on sd5203, see Patch 5 and 8. 7. Add Patch 9, all controller should contain "syscon" compatible string. 8. Add property "ranges" and update the example, see Patch 16. 9. Romove the labels in all examples. 10. other trival fixes are not mentioned. Please review Patch 1-9 first, other patches are not urgent and each of them is independent. v3 --> v4: 1. remove unexpected "\ No newline at end of file" of each new file. 2. discard the subdirectory "hi3620" and "hipxx", all files in the two directories are moved to the parent directory. 3. add two spaces for the below cases: - items: - const: hisilicon,sysctrl. //add two spaces 4. only list the compatible of boards in hisilicon.yaml, that is: 1) a compatible of one board 2) a compatible of one board + a compatible of one SoC 5. other trival fixes are not mentioned. v2 --> v3: 1. Convert hisilicon.txt to hisilicon.yaml. Because there are many kinds of Hisilicon controllers in it, so split each of them into a separate file first. Then I convert all of them to DT schema format, and also convert the other files in directory "../bindings/arm/hisilicon/". 2. Add Patch 1: remove a unused compatible name in hip01-ca9x2.dts This error is detected by hisilicon.yaml. The merge window of 5.10 is narrow now, so please review Patch 1-7 first. v1 --> v2: 1. add binding for SD5203 SoC, Patch 1 2. select DW_APB_ICTL instead of HISILICON_SD5203_VIC in Patch 2. Meanwhile, change the compatible of interrupt-controller to "snps,dw-apb-ictl" in Patch 4. 3. Fix the errors detected by dtbs_check. For example: add "reg" for cpu node, use lowercase a-f to describe address, add "baudclk" for "snps,dw-apb-uart". v1: Add SD5203 SoC config option and devicetree file, also enable its debug UART. Kefeng Wang (3): ARM: hisi: add support for SD5203 SoC ARM: debug: add UART early console support for SD5203 ARM: dts: add SD5203 dts Zhen Lei (14): dt-bindings: mfd: syscon: add some compatible strings for Hisilicon dt-bindings: arm: hisilicon: delete the descriptions of HiP05/HiP06 controllers dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema dt-bindings: arm: hisilicon: add binding for SD5203 SoC ARM: dts: hisilicon: fix ststem controller compatible node dt-bindings: arm: hisilicon: convert system controller bindings to json-schema dt-bindings: arm: hisilicon: convert hisilicon,cpuctrl bindings to json-schema dt-bindings: arm: hisilicon: convert hisilicon,pctrl bindings to json-schema dt-bindings: arm: hisilicon: convert hisilicon,hip04-fabric bindings to json-schema dt-bindings: arm: hisilicon: convert hisilicon,hip04-bootwrapper bindings to json-schema dt-bindings: arm: hisilicon: convert Hi6220 domain controller bindings to json-schema dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl bindings to json-schema dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema .../bindings/arm/hisilicon/controller/cpuctrl.yaml | 29 ++ .../hisilicon/controller/hi3798cv200-perictrl.yaml | 64 +++++ .../hisilicon/controller/hi6220-domain-ctrl.yaml | 68 +++++ .../hisilicon/controller/hip04-bootwrapper.yaml | 34 +++ .../arm/hisilicon/controller/hip04-fabric.yaml | 27 ++ .../bindings/arm/hisilicon/controller/pctrl.yaml | 34 +++ .../bindings/arm/hisilicon/controller/sysctrl.yaml | 110 +++++++ .../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 - .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 --- .../bindings/arm/hisilicon/hisilicon.txt | 319 --------------------- .../bindings/arm/hisilicon/hisilicon.yaml | 67 +++++ .../bindings/arm/hisilicon/low-pin-count.yaml | 61 ++++ Documentation/devicetree/bindings/mfd/syscon.yaml | 5 +- arch/arm/Kconfig.debug | 11 +- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/hi3620.dtsi | 2 +- arch/arm/boot/dts/hip04.dtsi | 2 +- arch/arm/boot/dts/sd5203.dts | 96 +++++++ arch/arm/mach-hisi/Kconfig | 16 +- 19 files changed, 622 insertions(+), 372 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml create mode 100644 arch/arm/boot/dts/sd5203.dts -- 1.8.3