| Message ID | 20201110114508.1197652-1-gregory.clement@bootlin.com |
|---|---|
| Headers | show |
| Series | MIPS: Add support for more mscc SoCs: Luton, Serval and Jaguar2 | expand |
On 10/11/2020 12:45:04+0100, Gregory CLEMENT wrote: > Add a device tree include file for the Microsemi Luton SoC which > belongs to same family of the Ocelot SoC. > > It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>. > > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> > --- > arch/mips/boot/dts/mscc/luton.dtsi | 116 +++++++++++++++++++++++++++++ > 1 file changed, 116 insertions(+) > create mode 100644 arch/mips/boot/dts/mscc/luton.dtsi > > diff --git a/arch/mips/boot/dts/mscc/luton.dtsi b/arch/mips/boot/dts/mscc/luton.dtsi > new file mode 100644 > index 000000000000..2a170b84c5a9 > --- /dev/null > +++ b/arch/mips/boot/dts/mscc/luton.dtsi > @@ -0,0 +1,116 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2020 Microsemi Corporation */ > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "mscc,luton"; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "mips,mips24KEc"; > + device_type = "cpu"; > + clocks = <&cpu_clk>; > + reg = <0>; > + }; > + }; > + > + aliases { > + serial0 = &uart0; > + }; > + > + cpuintc: interrupt-controller { > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-controller; > + compatible = "mti,cpu-interrupt-controller"; > + }; > + > + cpu_clk: cpu-clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <416666666>; > + }; > + > + ahb_clk: ahb-clk { > + compatible = "fixed-factor-clock"; > + #clock-cells = <0>; > + clocks = <&cpu_clk>; > + clock-div = <2>; > + clock-mult = <1>; > + }; > + > + ahb@60000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x60000000 0x20000000>; > + > + interrupt-parent = <&intc>; > + > + cpu_ctrl: syscon@10000000 { > + compatible = "mscc,ocelot-cpu-syscon", "syscon"; > + reg = <0x10000000 0x2c>; > + }; > + > + intc: interrupt-controller@10000084 { > + compatible = "mscc,luton-icpu-intr"; > + reg = <0x10000084 0x70>; > + #interrupt-cells = <1>; > + interrupt-controller; > + interrupt-parent = <&cpuintc>; > + interrupts = <2>; > + }; > + > + uart0: serial@10100000 { > + pinctrl-0 = <&uart_pins>; > + pinctrl-names = "default"; > + compatible = "ns16550a"; > + reg = <0x10100000 0x20>; > + interrupts = <6>; > + clocks = <&ahb_clk>; > + reg-io-width = <4>; > + reg-shift = <2>; > + > + status = "disabled"; > + }; > + > + i2c0: i2c@10100400 { > + compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; > + pinctrl-0 = <&i2c_pins>; > + pinctrl-names = "default"; > + reg = <0x10100400 0x100>, <0x100002a4 0x8>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <11>; > + clocks = <&ahb_clk>; > + > + status = "disabled"; > + }; > + > + gpio: pinctrl@70068 { > + compatible = "mscc,luton-pinctrl"; > + reg = <0x70068 0x28>; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&gpio 0 0 32>; > + interrupt-controller; > + interrupts = <13>; > + #interrupt-cells = <2>; > + > + i2c_pins: i2c-pins { > + pins = "GPIO_5", "GPIO_6"; > + function = "twi"; > + }; > + > + uart_pins: uart-pins { > + pins = "GPIO_30", "GPIO_31"; > + function = "uart"; > + }; > + > + }; > + }; > +}; > -- > 2.28.0 >
On 10/11/2020 12:45:06+0100, Gregory CLEMENT wrote: > Luton now has already an u-boot port so let's build FIT images. > > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> > --- > arch/mips/generic/Kconfig | 8 ++++++++ > arch/mips/generic/Platform | 1 + > arch/mips/generic/board-luton.its.S | 23 +++++++++++++++++++++++ > 3 files changed, 32 insertions(+) > create mode 100644 arch/mips/generic/board-luton.its.S > > diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig > index eb2a3fa9fcd7..e5a7a1314e71 100644 > --- a/arch/mips/generic/Kconfig > +++ b/arch/mips/generic/Kconfig > @@ -78,6 +78,14 @@ config FIT_IMAGE_FDT_OCELOT > from Microsemi in the FIT kernel image. > This requires u-boot on the platform. > > +config FIT_IMAGE_FDT_LUTON > + bool "Include FDT for Microsemi Luton development platforms" > + select SOC_VCOREIII > + help > + Enable this to include the FDT for the Luton development platforms > + from Microsemi in the FIT kernel image. > + This requires u-boot on the platform. > + > config BOARD_INGENIC > bool "Support boards based on Ingenic SoCs" > select MACH_INGENIC_GENERIC > diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform > index f8ef2f9d107e..4b6905daa39c 100644 > --- a/arch/mips/generic/Platform > +++ b/arch/mips/generic/Platform > @@ -20,4 +20,5 @@ its-y := vmlinux.its.S > its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S > its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S > its-$(CONFIG_FIT_IMAGE_FDT_OCELOT) += board-ocelot.its.S > +its-$(CONFIG_FIT_IMAGE_FDT_LUTON) += board-luton.its.S > its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S > diff --git a/arch/mips/generic/board-luton.its.S b/arch/mips/generic/board-luton.its.S > new file mode 100644 > index 000000000000..39a543f62f25 > --- /dev/null > +++ b/arch/mips/generic/board-luton.its.S > @@ -0,0 +1,23 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > +/ { > + images { > + fdt@luton_pcb091 { > + description = "MSCC Luton PCB091 Device Tree"; > + data = /incbin/("boot/dts/mscc/luton_pcb091.dtb"); > + type = "flat_dt"; > + arch = "mips"; > + compression = "none"; > + hash@0 { > + algo = "sha1"; > + }; > + }; > + }; > + > + configurations { > + pcb091 { > + description = "Luton Linux kernel"; > + kernel = "kernel@0"; > + fdt = "fdt@luton_pcb091"; > + }; > + }; > +}; > -- > 2.28.0 >
On Tue, Nov 10, 2020 at 12:44:59PM +0100, Gregory CLEMENT wrote: > Hello, > > Ocelot SoC belongs to a larger family of SoCs called VCoreIII. Luton, > Serval and Jaguar2 are part of this family and are added with this > series. > > This the second version with a few changes in device tree. > > To be able to run a linux kernel the irqchip support and the pinctrl > support are needed. Two series of patches adding this support has been > posted to their subsystem. However there is no build dependency > between them. > > Changelog: > v1 -> v2 > - Moved the changes in binding documentation from patch 8 to 2 > - Fixed i2c devices node name in jaguar2 device tree files > - Added Acked-by from Rob Herring > - Fixes few more devices tree nodes, now there is no more warning when > running "make W=1 dtbs" > > Gregory > > Gregory CLEMENT (9): > dt-bindings: mips: Add Luton > dt-bindings: mips: Add Serval and Jaguar2 > MIPS: mscc: Prepare configuration to handle more SoCs > MIPS: mscc: Fix configuration name for ocelot legacy boards > MIPS: mscc: Add luton dtsi > MIPS: mscc: Add luton PC0B91 device tree > MIPS: mscc: build FIT image for Luton > MIPS: mscc: Add jaguar2 support > MIPS: mscc: Add serval support > > .../devicetree/bindings/mips/mscc.txt | 2 +- > arch/mips/boot/dts/Makefile | 2 +- > arch/mips/boot/dts/mscc/Makefile | 11 +- > arch/mips/boot/dts/mscc/jaguar2.dtsi | 167 +++++++++++ > arch/mips/boot/dts/mscc/jaguar2_common.dtsi | 25 ++ > arch/mips/boot/dts/mscc/jaguar2_pcb110.dts | 267 ++++++++++++++++++ > arch/mips/boot/dts/mscc/jaguar2_pcb111.dts | 107 +++++++ > arch/mips/boot/dts/mscc/jaguar2_pcb118.dts | 57 ++++ > arch/mips/boot/dts/mscc/luton.dtsi | 116 ++++++++ > arch/mips/boot/dts/mscc/luton_pcb091.dts | 30 ++ > arch/mips/boot/dts/mscc/serval.dtsi | 153 ++++++++++ > arch/mips/boot/dts/mscc/serval_common.dtsi | 127 +++++++++ > arch/mips/boot/dts/mscc/serval_pcb105.dts | 17 ++ > arch/mips/boot/dts/mscc/serval_pcb106.dts | 17 ++ > arch/mips/generic/Kconfig | 37 ++- > arch/mips/generic/Platform | 3 + > arch/mips/generic/board-jaguar2.its.S | 40 +++ > arch/mips/generic/board-luton.its.S | 23 ++ > arch/mips/generic/board-serval.its.S | 24 ++ > 19 files changed, 1218 insertions(+), 7 deletions(-) > create mode 100644 arch/mips/boot/dts/mscc/jaguar2.dtsi > create mode 100644 arch/mips/boot/dts/mscc/jaguar2_common.dtsi > create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb110.dts > create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb111.dts > create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb118.dts > create mode 100644 arch/mips/boot/dts/mscc/luton.dtsi > create mode 100644 arch/mips/boot/dts/mscc/luton_pcb091.dts > create mode 100644 arch/mips/boot/dts/mscc/serval.dtsi > create mode 100644 arch/mips/boot/dts/mscc/serval_common.dtsi > create mode 100644 arch/mips/boot/dts/mscc/serval_pcb105.dts > create mode 100644 arch/mips/boot/dts/mscc/serval_pcb106.dts > create mode 100644 arch/mips/generic/board-jaguar2.its.S > create mode 100644 arch/mips/generic/board-luton.its.S > create mode 100644 arch/mips/generic/board-serval.its.S series applied to mips-next. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]