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[v2,0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654

Message ID 20210305153926.3479-1-p.yadav@ti.com
Headers show
Series Enable 8D-8D-8D mode on J721E, J7200, AM654 | expand

Message

Pratyush Yadav March 5, 2021, 3:39 p.m. UTC
Hi,

Now that the OSPI controller driver and the SPI NOR core have support
for 8D-8D-8D mode, the device tree can be updated to allow Octal DTR
transactions.

Pratyush Yadav (3):
  arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI
  arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI
  arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0

 .../arm64/boot/dts/ti/k3-am654-base-board.dts |  4 +--
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 17 +++++++++
 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi   | 36 +++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi   |  4 +--
 4 files changed, 57 insertions(+), 4 deletions(-)

--
2.30.0

Comments

Vignesh Raghavendra March 5, 2021, 4:12 p.m. UTC | #1
On 3/5/21 9:09 PM, Pratyush Yadav wrote:
> Set the Tx bus width to 8 so 8D-8D-8D mode can be selected. Change the
> frequency to 25 MHz. This is the frequency that the flash has been
> successfully tested with in Octal DTR mode. The total performance should
> still increase since 8D-8D-8D mode should be at least twice as fast as
> 1S-1S-8S mode.
> 
> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> ---
> 

Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>

> Notes:
>     No changes in v2.
> 
>  arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
> index fe3043943906..9e87fb313a54 100644
> --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
> @@ -483,9 +483,9 @@ &ospi0 {
>  	flash@0{
>  		compatible = "jedec,spi-nor";
>  		reg = <0x0>;
> -		spi-tx-bus-width = <1>;
> +		spi-tx-bus-width = <8>;
>  		spi-rx-bus-width = <8>;
> -		spi-max-frequency = <40000000>;
> +		spi-max-frequency = <25000000>;
>  		cdns,tshsl-ns = <60>;
>  		cdns,tsd2d-ns = <60>;
>  		cdns,tchsh-ns = <60>;
>
Nishanth Menon March 11, 2021, 2:17 p.m. UTC | #2
On Fri, 5 Mar 2021 21:09:23 +0530, Pratyush Yadav wrote:
> Now that the OSPI controller driver and the SPI NOR core have support

> for 8D-8D-8D mode, the device tree can be updated to allow Octal DTR

> transactions.

> 

> Pratyush Yadav (3):

>   arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI

>   arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI

>   arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0

> 

> [...]


Hi Pratyush Yadav,


I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI
      commit: 4c20ee99dd1a36ab89c6a8c51ed25e9328d8a8cc
[2/3] arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI
      commit: 7c172b30a540644fa53051e947d6712be5d6d6ce
[3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0
      commit: efbdf2e9183bd5e75c64d251c6b673ca61ea01b3


All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
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[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D)/Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D