| Message ID | 20210428134759.22076-1-cl@rock-chips.com |
|---|---|
| Headers | show |
| Series | arm64: dts: rockchip: add basic dtsi/dts files for RK3568 SoC | expand |
On Wed, 28 Apr 2021 14:50:02 +0100, <cl@rock-chips.com> wrote: > > From: Liang Chen <cl@rock-chips.com> > > RK3568 is a high-performance and low power quad-core application processor > designed for personal mobile internet device and AIoT equipment. This patch > add basic core dtsi file for it. > > We use scmi_clk for cortex-a55 instead of standard ARMCLK, so that > kernel/uboot/rtos can change cpu clk with the same code in ATF, and we will > enalbe a special high-performance PLL when high frequency is required. The > smci_clk code is in ATF, and clkid for cpu is 0, as below: > > cpu0: cpu@0 { > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x0>; > clocks = <&scmi_clk 0>; > }; > > Signed-off-by: Liang Chen <cl@rock-chips.com> > --- > .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 3111 +++++++++++++++++ > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 779 +++++ > 2 files changed, 3890 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi [...] > + gic: interrupt-controller@fd400000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ > + <0x0 0xfd460000 0 0xc0000>; /* GICR */ If this SoC has 4 CPUs, that's 4 redistributors. Given that GIC600 doesn't implement VLPIs, that's 128kB per redistributors. Why is GICR large enough for 6 CPUs here? Is that copy-pasted from another SoC? > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <3>; > + mbi-alias = <0x0 0xfd400000>; > + mbi-ranges = <296 24>; > + msi-controller; > + }; Glad to see that you found some spare SPIs to get MSIs going However, the whole point of mbi-alias (aka GICA in GIC600) is to be different from GICD and provide some isolation via an IOMMU. If I trust the TRM, if should be at 0xfd10000 in your implementation. Thanks, M.
Hi,
Question for rob+dt or others.
===
1: Given error:
/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dt.yaml: sram@10f000:
sram@0:compatible: None of ['arm,scmi-shmem'] are valid under the given
schema
From schema: /Documentation/devicetree/bindings/sram/sram.yaml
===
2: Given incorrect sram Example arm,scmi.txt that is in need to convert to
YAML:
sram@50000000 {
compatible = "mmio-sram";
reg = <0x0 0x50000000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x50000000 0x10000>;
cpu_scp_lpri: scp-shmem@0 {
===
sram@0
===
compatible = "arm,scmi-shmem";
reg = <0x0 0x200>;
};
cpu_scp_hpri: scp-shmem@200 {
===
sram@200
===
compatible = "arm,scmi-shmem";
reg = <0x200 0x200>;
};
};
===
Should "arm,scmi-shmem" also be added to sram.yaml ??
What to do with "arm,scmi.txt" then ??
patternProperties:
"^([a-z]*-)?sram(-section)?@[a-f0-9]+$":
type: object
description:
Each child of the sram node specifies a region of reserved memory.
properties:
compatible:
description:
Should contain a vendor specific string in the form
<vendor>,[<device>-]<usage>
contains:
enum:
- allwinner,sun4i-a10-sram-a3-a4
- allwinner,sun4i-a10-sram-c1
- allwinner,sun4i-a10-sram-d
- allwinner,sun9i-a80-smp-sram
- allwinner,sun50i-a64-sram-c
- amlogic,meson8-ao-arc-sram
- amlogic,meson8b-ao-arc-sram
- amlogic,meson8-smp-sram
- amlogic,meson8b-smp-sram
- amlogic,meson-gxbb-scp-shmem
- amlogic,meson-axg-scp-shmem
===
- arm,scmi-shmem
===
- renesas,smp-sram
- rockchip,rk3066-smp-sram
- samsung,exynos4210-sysram
- samsung,exynos4210-sysram-ns
- socionext,milbeaut-smp-sram
====
Given missing YAML documents for:
operating-points-v2
arm,pl330, arm,primecell
arm,scmi-smc
arm,scmi-shmem
rockchip,rk3568-pinctrl
For sort order and dtbs_check and for what's worth and fixed:
Reviewed-by: Johan Jonker <jbx6244@gmail.com>
On 4/28/21 3:50 PM, cl@rock-chips.com wrote:
> From: Liang Chen <cl@rock-chips.com>
>
> RK3568 is a high-performance and low power quad-core application processor
> designed for personal mobile internet device and AIoT equipment. This patch
> add basic core dtsi file for it.
>
> We use scmi_clk for cortex-a55 instead of standard ARMCLK, so that
> kernel/uboot/rtos can change cpu clk with the same code in ATF, and we will
> enalbe a special high-performance PLL when high frequency is required. The
> smci_clk code is in ATF, and clkid for cpu is 0, as below:
>
> cpu0: cpu@0 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x0>;
> clocks = <&scmi_clk 0>;
> };
>
> Signed-off-by: Liang Chen <cl@rock-chips.com>
> ---
[..]
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> new file mode 100644
> index 000000000000..7983fa13d93f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -0,0 +1,779 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
> + */
> +
> +#include <dt-bindings/clock/rk3568-cru.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/soc/rockchip,boot-mode.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> + compatible = "rockchip,rk3568";
> +
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + gpio0 = &gpio0;
> + gpio1 = &gpio1;
> + gpio2 = &gpio2;
> + gpio3 = &gpio3;
> + gpio4 = &gpio4;
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + serial5 = &uart5;
> + serial6 = &uart6;
> + serial7 = &uart7;
> + serial8 = &uart8;
> + serial9 = &uart9;
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x0 0x0>;
> + clocks = <&scmi_clk 0>;
> + enable-method = "psci";
> + operating-points-v2 = <&cpu0_opp_table>;
> + };
> +
> + cpu1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + operating-points-v2 = <&cpu0_opp_table>;
> + };
> +
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + operating-points-v2 = <&cpu0_opp_table>;
> + };
> +
> + cpu3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x0 0x300>;
> + enable-method = "psci";
> + operating-points-v2 = <&cpu0_opp_table>;
> + };
> + };
> +
> + cpu0_opp_table: cpu0-opp-table {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-408000000 {
> + opp-hz = /bits/ 64 <408000000>;
> + opp-microvolt = <900000 900000 1150000>;
> + clock-latency-ns = <40000>;
> + };
> +
> + opp-600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-microvolt = <900000 900000 1150000>;
> + };
> +
> + opp-816000000 {
> + opp-hz = /bits/ 64 <816000000>;
> + opp-microvolt = <900000 900000 1150000>;
> + opp-suspend;
> + };
> +
> + opp-1104000000 {
> + opp-hz = /bits/ 64 <1104000000>;
> + opp-microvolt = <900000 900000 1150000>;
> + };
> +
> + opp-1416000000 {
> + opp-hz = /bits/ 64 <1416000000>;
> + opp-microvolt = <900000 900000 1150000>;
> + };
> +
> + opp-1608000000 {
> + opp-hz = /bits/ 64 <1608000000>;
> + opp-microvolt = <975000 975000 1150000>;
> + };
> +
> + opp-1800000000 {
> + opp-hz = /bits/ 64 <1800000000>;
> + opp-microvolt = <1050000 1050000 1150000>;
> + };
> +
> + opp-1992000000 {
> + opp-hz = /bits/ 64 <1992000000>;
> + opp-microvolt = <1150000 1150000 1150000>;
> + };
> + };
> +
> + firmware {
> + scmi: scmi {
> + compatible = "arm,scmi-smc";
> + arm,smc-id = <0x82000010>;
> + shmem = <&scmi_shmem>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + scmi_clk: protocol@14 {
> + reg = <0x14>;
> + #clock-cells = <1>;
> + };
> + };
> +
Remove empty line.
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a55-pmu";
> + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + arm,no-tick-in-suspend;
> + };
> +
> + xin24m: xin24m {
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "xin24m";
> + #clock-cells = <0>;
> + };
> +
> + xin32k: xin32k {
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "xin32k";
> + pinctrl-0 = <&clk32k_out0>;
> + pinctrl-names = "default";
> + #clock-cells = <0>;
> + };
> +
> + sram@10f000 {
> + compatible = "mmio-sram";
> + reg = <0x0 0x0010f000 0x0 0x100>;
> +
Remove empty line.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0 0x0010f000 0x100>;
Is this correct ?
> +
> + scmi_shmem: sram@0 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x0 0x100>;
> + };
> + };
> +
> + gic: interrupt-controller@fd400000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
> + <0x0 0xfd460000 0 0xc0000>; /* GICR */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + mbi-alias = <0x0 0xfd400000>;
> + mbi-ranges = <296 24>;
> + msi-controller;
> + };
> +
> + pmugrf: syscon@fdc20000 {
> + compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
> + reg = <0x0 0xfdc20000 0x0 0x10000>;
> + };
> +
> + grf: syscon@fdc60000 {
> + compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
> + reg = <0x0 0xfdc60000 0x0 0x10000>;
> + };
> +
> + pmucru: clock-controller@fdd00000 {
> + compatible = "rockchip,rk3568-pmucru";
> + reg = <0x0 0xfdd00000 0x0 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + cru: clock-controller@fdd20000 {
> + compatible = "rockchip,rk3568-cru";
> + reg = <0x0 0xfdd20000 0x0 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + i2c0: i2c@fdd40000 {
> + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
> + reg = <0x0 0xfdd40000 0x0 0x1000>;
> + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
> + clock-names = "i2c", "pclk";
> + pinctrl-0 = <&i2c0_xfer>;
> + pinctrl-names = "default";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + uart0: serial@fdd50000 {
> + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
> + reg = <0x0 0xfdd50000 0x0 0x100>;
> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
> + clock-names = "baudclk", "apb_pclk";
> + dmas = <&dmac0 0>, <&dmac0 1>;
> + pinctrl-0 = <&uart0_xfer>;
> + pinctrl-names = "default";
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + pwm0: pwm@fdd70000 {
> + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
> + reg = <0x0 0xfdd70000 0x0 0x10>;
> + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
> + clock-names = "pwm", "pclk";
> + pinctrl-0 = <&pwm0m0_pins>;
> + pinctrl-names = "active";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1: pwm@fdd70010 {
> + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
> + reg = <0x0 0xfdd70010 0x0 0x10>;
> + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
> + clock-names = "pwm", "pclk";
> + pinctrl-0 = <&pwm1m0_pins>;
> + pinctrl-names = "active";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2: pwm@fdd70020 {
> + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
> + reg = <0x0 0xfdd70020 0x0 0x10>;
> + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
> + clock-names = "pwm", "pclk";
> + pinctrl-0 = <&pwm2m0_pins>;
> + pinctrl-names = "active";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm3: pwm@fdd70030 {
> + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
> + reg = <0x0 0xfdd70030 0x0 0x10>;
> + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
> + clock-names = "pwm", "pclk";
> + pinctrl-0 = <&pwm3_pins>;
> + pinctrl-names = "active";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + sdmmc2: mmc@fe000000 {
> + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
> + reg = <0x0 0xfe000000 0x0 0x4000>;
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
> + <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + fifo-depth = <0x100>;
> + max-frequency = <150000000>;
> + resets = <&cru SRST_SDMMC2>;
> + reset-names = "reset";
> + status = "disabled";
> + };
> +
> + sdmmc0: mmc@fe2b0000 {
> + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
> + reg = <0x0 0xfe2b0000 0x0 0x4000>;
> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
> + <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + fifo-depth = <0x100>;
> + max-frequency = <150000000>;
> + resets = <&cru SRST_SDMMC0>;
> + reset-names = "reset";
> + status = "disabled";
> + };
> +
> + sdmmc1: mmc@fe2c0000 {
> + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
> + reg = <0x0 0xfe2c0000 0x0 0x4000>;
> + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
> + <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + fifo-depth = <0x100>;
> + max-frequency = <150000000>;
> + resets = <&cru SRST_SDMMC1>;
> + reset-names = "reset";
> + status = "disabled";
> + };
> +
> + sdhci: mmc@fe310000 {
mmc@fe310000: rockchip,txclk-tapnum: missing size tag in [[8]]
On Thu, 29 Apr 2021 02:13:35 +0100, 陈亮 <cl@rock-chips.com> wrote: > > Hi Marc, > > 在 2021/4/28 下午11:06, Marc Zyngier 写道: > > On Wed, 28 Apr 2021 14:50:02 +0100, > > <cl@rock-chips.com> wrote: > >> From: Liang Chen <cl@rock-chips.com> > >> > >> RK3568 is a high-performance and low power quad-core application processor > >> designed for personal mobile internet device and AIoT equipment. This patch > >> add basic core dtsi file for it. > >> > >> We use scmi_clk for cortex-a55 instead of standard ARMCLK, so that > >> kernel/uboot/rtos can change cpu clk with the same code in ATF, and we will > >> enalbe a special high-performance PLL when high frequency is required. The > >> smci_clk code is in ATF, and clkid for cpu is 0, as below: > >> > >> cpu0: cpu@0 { > >> device_type = "cpu"; > >> compatible = "arm,cortex-a55"; > >> reg = <0x0 0x0>; > >> clocks = <&scmi_clk 0>; > >> }; > >> > >> Signed-off-by: Liang Chen <cl@rock-chips.com> > >> --- > >> .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 3111 +++++++++++++++++ > >> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 779 +++++ > >> 2 files changed, 3890 insertions(+) > >> create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > >> create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi > > [...] > > > >> + gic: interrupt-controller@fd400000 { > >> + compatible = "arm,gic-v3"; > >> + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ > >> + <0x0 0xfd460000 0 0xc0000>; /* GICR */ > > If this SoC has 4 CPUs, that's 4 redistributors. Given that GIC600 > > doesn't implement VLPIs, that's 128kB per redistributors. Why is GICR > > large enough for 6 CPUs here? Is that copy-pasted from another SoC? > Copy from rk3399, sorry. > >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > >> + interrupt-controller; > >> + #interrupt-cells = <3>; > >> + mbi-alias = <0x0 0xfd400000>; > >> + mbi-ranges = <296 24>; > >> + msi-controller; > >> + }; > > Glad to see that you found some spare SPIs to get MSIs going > > > > However, the whole point of mbi-alias (aka GICA in GIC600) is to be > > different from GICD and provide some isolation via an IOMMU. If I > > trust the TRM, if should be at 0xfd10000 in your implementation. > > But in the ./devicetree/bindings/interrupt-controller/arm,gic-v3.yaml, say: > > mbi-alias: > description: > Address property. Base address of an alias of the *GICD* region > containing > only the {SET,CLR}SPI registers to be used if isolation is required, > and if supported by the HW. [recurring theme: I happen to know about this section of the binding, having written the original myself] How does that contradict my comment? GIC600's GICA page only contains the four {SET,CLR}_SPI registers, as expected (see section 4.3 in the TRM[1]), and the address is computed using table 4-1 "Register map pages" of the same document. Please either fix the DT or explain why the GICA distributor alias isn't usable. M. [1] https://documentation-service.arm.com/static/5e7ddddacbfe76649ba53034
From: Liang Chen <cl@rock-chips.com> v1: 1. add some dt-bindings for RK3568 devices. 2. add core dtsi for RK3568 SoC. 3. add basic dts for RK3568 EVB v2: 1. sort device nodes by some rules. v3: 1. make ARCH=arm64 dtbs_check, then fix some errors and add some documents. Liang Chen (10): dt-bindings: i2c: i2c-rk3x: add description for rk3568 dt-bindings: serial: snps-dw-apb-uart: add description for rk3568 dt-bindings: mmc: rockchip-dw-mshc: add description for rk3568 dt-bindings: watchdog: dw-wdt: add description for rk3568 dt-bindings: pwm: rockchip: add description for rk3568 dt-bindings: gpio: change items restriction of clock for rockchip,gpio-bank dt-bindings: soc: rockchip: Convert grf.txt to YAML arm64: dts: rockchip: add generic pinconfig settings used by most Rockchip socs arm64: dts: rockchip: add core dtsi for RK3568 SoC arm64: dts: rockchip: add basic dts for RK3568 EVB .../devicetree/bindings/arm/rockchip.yaml | 5 + .../bindings/gpio/rockchip,gpio-bank.yaml | 3 +- .../devicetree/bindings/i2c/i2c-rk3x.yaml | 1 + .../bindings/mmc/rockchip-dw-mshc.yaml | 9 +- .../devicetree/bindings/pwm/pwm-rockchip.yaml | 1 + .../bindings/serial/snps-dw-apb-uart.yaml | 1 + .../devicetree/bindings/soc/rockchip/grf.txt | 61 - .../devicetree/bindings/soc/rockchip/grf.yaml | 58 + .../bindings/watchdog/snps,dw-wdt.yaml | 1 + arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3568-evb1-v10.dts | 80 + .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 3111 +++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 789 +++++ .../boot/dts/rockchip/rockchip-pinconf.dtsi | 344 ++ 14 files changed, 4395 insertions(+), 70 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/grf.txt create mode 100644 Documentation/devicetree/bindings/soc/rockchip/grf.yaml create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi