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[0/5] phy: ralink: mt7621-pci-phy: some improvements

Message ID 20210506111531.21978-1-sergio.paracuellos@gmail.com
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Series phy: ralink: mt7621-pci-phy: some improvements | expand

Message

Sergio Paracuellos May 6, 2021, 11:15 a.m. UTC 
Hi all,

This series contains some improvements in the pci phy driver
for MT7621 SoCs.

MT7621 SoC clock driver has already mainlined in
'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")'

Because of this we can update schema documentation and device tree
to add related clock entries and avoid custom architecture code
in favour of using the clock kernel framework to retrieve clock 
frequency needed to properly configure the PCIe related Phys.

After this changes there is no problem to properly enable this
driver for COMPILE_TEST.

Configuration has also modified from 'tristate' to 'bool' depending
on PCI_MT7621 which seems to have more sense.

Thanks in advance for your time.

Best regards,
    Sergio Paracuellos


Sergio Paracuellos (5):
  staging: mt7621-dts: use clock in pci phy nodes
  dt-bindings: phy: mediatek,mt7621-pci-phy: add clock entries
  phy: ralink: phy-mt7621-pci: use kernel clock APIS
  phy: ralink: Kconfig: enable COMPILE_TEST on mt7621-pci-phy driver
  phy: ralink: Kconfig: convert mt7621-pci-phy into 'bool'

 .../bindings/phy/mediatek,mt7621-pci-phy.yaml | 12 +++++++
 drivers/phy/ralink/Kconfig                    |  4 +--
 drivers/phy/ralink/phy-mt7621-pci.c           | 33 +++++++++++--------
 drivers/staging/mt7621-dts/mt7621.dtsi        |  4 +++
 4 files changed, 38 insertions(+), 15 deletions(-)