From patchwork Sat Jul 10 01:32:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 472318 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp822063jao; Fri, 9 Jul 2021 18:33:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw3aQJUKo6PPtIAz7Seyv/z7wgdPsEUMUKUmJiMtbhQY9NPe4rdg1nkL9tVi74yNo/TVfAf X-Received: by 2002:a50:e79b:: with SMTP id b27mr44412529edn.267.1625880798333; Fri, 09 Jul 2021 18:33:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625880798; cv=none; d=google.com; s=arc-20160816; b=qkRmdTeNtYUa5X9qKC0Yt6BabXtYsKlVGcHrqij/6Xb9saHQ1yGXIdh7wFUJpSnqK9 w623DQhfVNYWlFXOlfBBufxfhLcY/aL3we0S7gGx7GtrCOaurD+ydEEvywuMvNT8u7S0 bX3twnALHzZGcEq6dgEIw5Pb0Kk+VedmHnOqPwPBnspC520zZBIzH13DN3NsJdfJTPMz GL3P+snDc6XYGuj8ewGdxZ1ODjre6Xug+YSHu+1VJoJYJAsZT1nomMu5zpFWz7ZiP6YY XJiqLrcFMqu+1SeFwwbiL1iK011gZ9LmJZx/murgFVkGK0afDU5Oc0g2bevPL11tGQqB y8Nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=UZvbJ8ZUJ5TOQauPo5aJpdbPhjigM8gpXKGnojAJE1A=; b=Z4TPG9Bd0iFpccxFWOAqaqSf220ETwNJNianwELn937/OugbGWU19UOJalkdxCMNWJ VvVhsWR+ykVrrvytcGfSEmiWbzBvEUGUFo51+uOhWVwVajNNinj3dqZPCdTWO8291xV5 8KuWfEbprSswko52zH9EAKbgLwjd3HaRgKlI3pcEu7fRZjvpDbCrIviscOJ3l2yfJn2W yqPZ3VgfU1cRYPBqfePGTymhsLLBBLaa+H0izycpySz1Ius2VlnIEoLLZZMGXW8I1twV SYdCU8gmVc0GQ9fKEIQVJ7V12fcRmqKyB8kni0y7SnYCjCH8gBzjxaTYTYVzGO0qTFqX FV0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WIIIXCH/"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dz14si9450283edb.241.2021.07.09.18.33.17; Fri, 09 Jul 2021 18:33:18 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WIIIXCH/"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229703AbhGJBfm (ORCPT + 7 others); Fri, 9 Jul 2021 21:35:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230317AbhGJBfl (ORCPT ); Fri, 9 Jul 2021 21:35:41 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BC4EC0613E9 for ; Fri, 9 Jul 2021 18:32:57 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id b40so10898551ljf.12 for ; Fri, 09 Jul 2021 18:32:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=UZvbJ8ZUJ5TOQauPo5aJpdbPhjigM8gpXKGnojAJE1A=; b=WIIIXCH/0grjnJfRVQQWRPY6PMIz9weSlcKEnahD5UjpZoIJphzg1KtFuTPiuNIBTW 6eZyNSFf9ZUtRUYyy5XQQwiF7+U3xNaYiYkcTdr3vU1pP4W6PdSxfLW+RTuWueekizAS EGJpOTFbp6qTH+4wJfwxxEQWgNz2j4YLbNPGtPJRQ9F1FE9b7dkXAx87f0ipLJ5OEAxV ctj0+CRlMay/zvLZEyTwHEb5N5OdZXBZ0CvcMLPIlqkmZtCrhqWLpIxXCMQmu/ObxgmD TpaK4Ndhh9DbrMjKSJ2le3OBpHUHIni84De5YScp/fE+zpAzjCibetBlYWAc0Hrg7td1 E2mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=UZvbJ8ZUJ5TOQauPo5aJpdbPhjigM8gpXKGnojAJE1A=; b=cUcIhMgJlzP4JzocfcFF9g5BqL1UoFuPQq7JY+jq6M4FqA1BaQAHbQqdgtVXny60Pm ivnp/nzoI7RxAfrwmvpOXrK/DTnrWpQfbo0ddz02i5pam013tUUQAJlc87V2TQUaSMUf 5W9oe1O+Pg+EuZYQGjOt8+yZRo0DSoXbLlE6Fc7xTLW1ieChB7KrUMjYxt0SHo/3IvoA gnOdOzJ6mnSTMpMCuCwAN8oGsU1iK3OE6FLquNeCeOF6RT34ZjnLS6/2Fhpux5pLhTTl xjA7n03NRgPpW2qB0fOIcBodN1ak3z6z7DKBgGHPZR4J6wmWuu6dy4fFuK8oY6E+5gUk MJUQ== X-Gm-Message-State: AOAM532BnPzAI7hJmffWr4Qitel0xAKtexPU0xct9fNKoy7L7Gf3dKm7 iAwuac2Ck31GheJPut9+QNYxhQ== X-Received: by 2002:a2e:5812:: with SMTP id m18mr5683932ljb.327.1625880775204; Fri, 09 Jul 2021 18:32:55 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p13sm588788lfh.206.2021.07.09.18.32.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 18:32:54 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v4 0/6] clk: qcom: use power-domain for sm8250's clock controllers Date: Sat, 10 Jul 2021 04:32:47 +0300 Message-Id: <20210710013253.1134341-1-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On SM8250 both the display and video clock controllers are powered up by the MMCX power domain. Handle this by linking clock controllers to the proper power domain, and using runtime power management to enable and disable the MMCX power domain. Dependencies: - https://lore.kernel.org/linux-pm/20210603093438.138705-1-ulf.hansson@linaro.org/ (merged in 5.14) - https://lore.kernel.org/linux-arm-msm/20210703005416.2668319-1-bjorn.andersson@linaro.org/ (pending) Changes since v3: - Wrap gdsc_enable/gdsc_disable into pm_runtime_get/put calls rather than calling pm_runtime_get in gdsc_enabled and _put in gdsc_disable - Squash gdsc patches together to remove possible dependencies between two patches. Changes since v2: - Move pm_runtime calls from generic genpd code to the gdsc code for now (as suggested by Ulf & Bjorn) Changes since v1: - Rebase on top of Bjorn's patches, removing the need for setting performance state directly. - Move runtime PM calls from GDSC code to generic genpd code. - Always call pm_runtime_enable in the Qualcomm generic clock controller code. - Register GDSC power domains as subdomains of the domain powering the clock controller if there is one. ---------------------------------------------------------------- Dmitry Baryshkov (6): dt-bindings: clock: qcom,dispcc-sm8x50: add mmcx power domain dt-bindings: clock: qcom,videocc: add mmcx power domain clk: qcom: gdsc: enable optional power domain support arm64: dts: qcom: sm8250: remove mmcx regulator clk: qcom: dispcc-sm8250: stop using mmcx regulator clk: qcom: videocc-sm8250: stop using mmcx regulator .../bindings/clock/qcom,dispcc-sm8x50.yaml | 7 +++ .../devicetree/bindings/clock/qcom,videocc.yaml | 7 +++ arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +--- drivers/clk/qcom/common.c | 37 ++++++++++-- drivers/clk/qcom/dispcc-sm8250.c | 1 - drivers/clk/qcom/gdsc.c | 67 +++++++++++++++++++++- drivers/clk/qcom/gdsc.h | 2 + drivers/clk/qcom/videocc-sm8250.c | 4 -- 8 files changed, 113 insertions(+), 23 deletions(-)