| Message ID | 20210712100317.23298-1-steven_lee@aspeedtech.com |
|---|---|
| Headers | show |
| Series | ASPEED sgpio driver enhancement. | expand |
On Mon, Jul 12, 2021 at 12:03 PM Steven Lee <steven_lee@aspeedtech.com> wrote: > > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one > with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that > supports up to 80 pins. > In the current driver design, the max number of sgpio pins is hardcoded > in macro MAX_NR_HW_SGPIO and the value is 80. > > For supporting sgpio master interfaces of AST2600 SoC, the patch series > contains the following enhancement: > - Convert txt dt-bindings to yaml. > - Update aspeed-g6 dtsi to support the enhanced sgpio. > - Support muiltiple SGPIO master interfaces. > - Support up to 128 pins by dts ngpios property. > - Pair input/output GPIOs instead of using 0 as GPIO input pin base and > MAX_NR_HW_SGPIO as GPIO output pin base. > - Support wdt reset tolerance. > - Fix irq_chip issues which causes multiple sgpio devices use the same > irq_chip data. > - Replace all of_*() APIs with device_*(). > > Changes from v5: > * Squash v5 patch-05 and patch-06 to one patch. > * Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio > input/output pin base are determined by ngpios. > For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original > pin order is as follows: > Input: > 0 1 2 3 ... 9 > Output: > 80 81 82 ... 89 > > With the new design, pin order is changed as follows: > Input: > 0 2 4 6 ... 18(ngpios * 2 - 2) > Output: > 1 3 5 7 ... 19(ngpios * 2 - 1) > * Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by > ast2600-sgpiom. > * Fix coding style issues. > > Changes from v4: > * Remove ngpios from dtsi > * Add ast2400 and ast2500 platform data. > * Remove unused macros. > * Add ngpios check in a separate patch. > * Fix coding style issues. > > Changes from v3: > * Split dt-bindings patch to 2 patches > * Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128 > * Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80 > * Correct the typo in commit messages. > * Fix coding style issues. > * Replace all of_*() APIs with device_*(). > > Changes from v2: > * Remove maximum/minimum of ngpios from bindings. > * Remove max-ngpios from bindings and dtsi. > * Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and > driver. > * Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max > number of available gpio pins are different. > * Modify functions to pass aspeed_sgpio struct instead of passing > max_ngpios. > * Split sgpio driver patch to 3 patches > > Changes from v1: > * Fix yaml format issues. > * Fix issues reported by kernel test robot. > > Please help to review. > > Thanks, > Steven > > Steven Lee (9): > dt-bindings: aspeed-sgpio: Convert txt bindings to yaml. > dt-bindings: aspeed-sgpio: Add ast2600 sgpio > ARM: dts: aspeed-g6: Add SGPIO node. > ARM: dts: aspeed-g5: Remove ngpios from sgpio node. > gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support > gpio: gpio-aspeed-sgpio: Add set_config function > gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct > gpio: gpio-aspeed-sgpio: Use generic device property APIs > gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8. > > .../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++ > .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ----- > arch/arm/boot/dts/aspeed-g5.dtsi | 1 - > arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++ > drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++------- > 5 files changed, 215 insertions(+), 115 deletions(-) > create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml > delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt > > -- > 2.17.1 > The series looks good to me. Can the DTS and GPIO patches go into v5.15 separately? Bart
The 07/21/2021 21:27, Bartosz Golaszewski wrote: > On Mon, Jul 12, 2021 at 12:03 PM Steven Lee <steven_lee@aspeedtech.com> wrote: > > > > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one > > with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that > > supports up to 80 pins. > > In the current driver design, the max number of sgpio pins is hardcoded > > in macro MAX_NR_HW_SGPIO and the value is 80. > > > > For supporting sgpio master interfaces of AST2600 SoC, the patch series > > contains the following enhancement: > > - Convert txt dt-bindings to yaml. > > - Update aspeed-g6 dtsi to support the enhanced sgpio. > > - Support muiltiple SGPIO master interfaces. > > - Support up to 128 pins by dts ngpios property. > > - Pair input/output GPIOs instead of using 0 as GPIO input pin base and > > MAX_NR_HW_SGPIO as GPIO output pin base. > > - Support wdt reset tolerance. > > - Fix irq_chip issues which causes multiple sgpio devices use the same > > irq_chip data. > > - Replace all of_*() APIs with device_*(). > > > > Changes from v5: > > * Squash v5 patch-05 and patch-06 to one patch. > > * Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio > > input/output pin base are determined by ngpios. > > For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original > > pin order is as follows: > > Input: > > 0 1 2 3 ... 9 > > Output: > > 80 81 82 ... 89 > > > > With the new design, pin order is changed as follows: > > Input: > > 0 2 4 6 ... 18(ngpios * 2 - 2) > > Output: > > 1 3 5 7 ... 19(ngpios * 2 - 1) > > * Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by > > ast2600-sgpiom. > > * Fix coding style issues. > > > > Changes from v4: > > * Remove ngpios from dtsi > > * Add ast2400 and ast2500 platform data. > > * Remove unused macros. > > * Add ngpios check in a separate patch. > > * Fix coding style issues. > > > > Changes from v3: > > * Split dt-bindings patch to 2 patches > > * Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128 > > * Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80 > > * Correct the typo in commit messages. > > * Fix coding style issues. > > * Replace all of_*() APIs with device_*(). > > > > Changes from v2: > > * Remove maximum/minimum of ngpios from bindings. > > * Remove max-ngpios from bindings and dtsi. > > * Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and > > driver. > > * Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max > > number of available gpio pins are different. > > * Modify functions to pass aspeed_sgpio struct instead of passing > > max_ngpios. > > * Split sgpio driver patch to 3 patches > > > > Changes from v1: > > * Fix yaml format issues. > > * Fix issues reported by kernel test robot. > > > > Please help to review. > > > > Thanks, > > Steven > > > > Steven Lee (9): > > dt-bindings: aspeed-sgpio: Convert txt bindings to yaml. > > dt-bindings: aspeed-sgpio: Add ast2600 sgpio > > ARM: dts: aspeed-g6: Add SGPIO node. > > ARM: dts: aspeed-g5: Remove ngpios from sgpio node. > > gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support > > gpio: gpio-aspeed-sgpio: Add set_config function > > gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct > > gpio: gpio-aspeed-sgpio: Use generic device property APIs > > gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8. > > > > .../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++ > > .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ----- > > arch/arm/boot/dts/aspeed-g5.dtsi | 1 - > > arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++ > > drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++------- > > 5 files changed, 215 insertions(+), 115 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml > > delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt > > > > -- > > 2.17.1 > > > > The series looks good to me. Can the DTS and GPIO patches go into > v5.15 separately? > Hi Bart, Thanks for the review. Shall we do anything to make the patches go into v5.15 or wait for picking-up? Steven > Bart
On Fri, Jul 23, 2021 at 5:16 AM Steven Lee <steven_lee@aspeedtech.com> wrote: > > The 07/21/2021 21:27, Bartosz Golaszewski wrote: > > On Mon, Jul 12, 2021 at 12:03 PM Steven Lee <steven_lee@aspeedtech.com> wrote: > > > > > > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one > > > with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that > > > supports up to 80 pins. > > > In the current driver design, the max number of sgpio pins is hardcoded > > > in macro MAX_NR_HW_SGPIO and the value is 80. > > > > > > For supporting sgpio master interfaces of AST2600 SoC, the patch series > > > contains the following enhancement: > > > - Convert txt dt-bindings to yaml. > > > - Update aspeed-g6 dtsi to support the enhanced sgpio. > > > - Support muiltiple SGPIO master interfaces. > > > - Support up to 128 pins by dts ngpios property. > > > - Pair input/output GPIOs instead of using 0 as GPIO input pin base and > > > MAX_NR_HW_SGPIO as GPIO output pin base. > > > - Support wdt reset tolerance. > > > - Fix irq_chip issues which causes multiple sgpio devices use the same > > > irq_chip data. > > > - Replace all of_*() APIs with device_*(). > > > > > > Changes from v5: > > > * Squash v5 patch-05 and patch-06 to one patch. > > > * Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio > > > input/output pin base are determined by ngpios. > > > For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original > > > pin order is as follows: > > > Input: > > > 0 1 2 3 ... 9 > > > Output: > > > 80 81 82 ... 89 > > > > > > With the new design, pin order is changed as follows: > > > Input: > > > 0 2 4 6 ... 18(ngpios * 2 - 2) > > > Output: > > > 1 3 5 7 ... 19(ngpios * 2 - 1) > > > * Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by > > > ast2600-sgpiom. > > > * Fix coding style issues. > > > > > > Changes from v4: > > > * Remove ngpios from dtsi > > > * Add ast2400 and ast2500 platform data. > > > * Remove unused macros. > > > * Add ngpios check in a separate patch. > > > * Fix coding style issues. > > > > > > Changes from v3: > > > * Split dt-bindings patch to 2 patches > > > * Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128 > > > * Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80 > > > * Correct the typo in commit messages. > > > * Fix coding style issues. > > > * Replace all of_*() APIs with device_*(). > > > > > > Changes from v2: > > > * Remove maximum/minimum of ngpios from bindings. > > > * Remove max-ngpios from bindings and dtsi. > > > * Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and > > > driver. > > > * Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max > > > number of available gpio pins are different. > > > * Modify functions to pass aspeed_sgpio struct instead of passing > > > max_ngpios. > > > * Split sgpio driver patch to 3 patches > > > > > > Changes from v1: > > > * Fix yaml format issues. > > > * Fix issues reported by kernel test robot. > > > > > > Please help to review. > > > > > > Thanks, > > > Steven > > > > > > Steven Lee (9): > > > dt-bindings: aspeed-sgpio: Convert txt bindings to yaml. > > > dt-bindings: aspeed-sgpio: Add ast2600 sgpio > > > ARM: dts: aspeed-g6: Add SGPIO node. > > > ARM: dts: aspeed-g5: Remove ngpios from sgpio node. > > > gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support > > > gpio: gpio-aspeed-sgpio: Add set_config function > > > gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct > > > gpio: gpio-aspeed-sgpio: Use generic device property APIs > > > gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8. > > > > > > .../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++ > > > .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ----- > > > arch/arm/boot/dts/aspeed-g5.dtsi | 1 - > > > arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++ > > > drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++------- > > > 5 files changed, 215 insertions(+), 115 deletions(-) > > > create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml > > > delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt > > > > > > -- > > > 2.17.1 > > > > > > > The series looks good to me. Can the DTS and GPIO patches go into > > v5.15 separately? > > > > Hi Bart, > > Thanks for the review. > Shall we do anything to make the patches go into v5.15 or wait for picking-up? > > Steven > > > Bart It's more of a question to the relevant SoC maintainers. Joel, Andrew: can I take the GPIO patches through the GPIO tree and you'll take the ARM patches separately into v5.15? Bartosz
On Mon, Jul 12, 2021 at 12:03 PM Steven Lee <steven_lee@aspeedtech.com> wrote: > sgpio-aspeed bindings should be converted to yaml format. > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> > Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
On Mon, Jul 12, 2021 at 12:04 PM Steven Lee <steven_lee@aspeedtech.com> wrote: > The maximum number of gpio pins of SoC is hardcoded as 80 and the gpio pin > count mask for GPIO Configuration register is hardcode as GENMASK(9,6). > However, AST2600 has 2 sgpio master interfaces, one of them supports up > to 128 gpio pins and pin count mask of GPIO Configuration Register is 5 > bits. > > The patch adds ast2600 compatibles, removes MAX_NR_HW_SGPIO and > corresponding design to make the gpio input/output pin base are determined > by ngpios. > The patch also removed hardcoded pin mask and adds ast2400, ast2500, > ast2600 platform data that include gpio pin count mask for GPIO > Configuration Register. > > The original pin order is as follows: > (suppose MAX_NR_HW_SGPIO is 80 and ngpios is 10 as well) > Input: > 0 1 2 3 ... 9 > Output: > 80 81 82 ... 89 > > The new pin order is as follows: > Input: > 0 2 4 6 ... 18 > Output: > 1 3 5 7 ... 19 > > SGPIO pin id and input/output pin mapping is as follows: > SGPIO0(0,1), SGPIO1(2,3), ..., SGPIO79(158,159) > > For example: > Access SGPIO5(10,11) > Get SGPIO pin 5 (suppose sgpio chip id is 2) > gpioget 2 10 > > Set SGPIO pin 5 (suppose sgpio chip id is 2) > gpioset 2 11=1 > gpioset 2 11=0 > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Nice use of match data. This is exactly how it shall be done. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
On Mon, Jul 12, 2021 at 12:04 PM Steven Lee <steven_lee@aspeedtech.com> wrote: > The current design initializes irq->chip from a global irqchip struct, > which causes multiple sgpio devices use the same irq_chip. > The patch moves irq_chip to aspeed_sgpio struct for initializing > irq_chip from their private gpio struct. > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> > Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
On Mon, Jul 12, 2021 at 12:04 PM Steven Lee <steven_lee@aspeedtech.com> wrote: > Add an else-if condition in the probe function to check whether ngpios is > multiple of 8. > Per AST datasheet, numbers of available serial GPIO pins in Serial GPIO > Configuration Register must be n bytes. For instance, if n = 1, it means > AST SoC supports 8 GPIO pins. > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> > Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
On Fri, 23 Jul 2021, at 17:00, Bartosz Golaszewski wrote: > On Fri, Jul 23, 2021 at 5:16 AM Steven Lee <steven_lee@aspeedtech.com> wrote: > > > > The 07/21/2021 21:27, Bartosz Golaszewski wrote: > > > On Mon, Jul 12, 2021 at 12:03 PM Steven Lee <steven_lee@aspeedtech.com> wrote: > > > > > > > > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one > > > > with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that > > > > supports up to 80 pins. > > > > In the current driver design, the max number of sgpio pins is hardcoded > > > > in macro MAX_NR_HW_SGPIO and the value is 80. > > > > > > > > For supporting sgpio master interfaces of AST2600 SoC, the patch series > > > > contains the following enhancement: > > > > - Convert txt dt-bindings to yaml. > > > > - Update aspeed-g6 dtsi to support the enhanced sgpio. > > > > - Support muiltiple SGPIO master interfaces. > > > > - Support up to 128 pins by dts ngpios property. > > > > - Pair input/output GPIOs instead of using 0 as GPIO input pin base and > > > > MAX_NR_HW_SGPIO as GPIO output pin base. > > > > - Support wdt reset tolerance. > > > > - Fix irq_chip issues which causes multiple sgpio devices use the same > > > > irq_chip data. > > > > - Replace all of_*() APIs with device_*(). > > > > > > > > Changes from v5: > > > > * Squash v5 patch-05 and patch-06 to one patch. > > > > * Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio > > > > input/output pin base are determined by ngpios. > > > > For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original > > > > pin order is as follows: > > > > Input: > > > > 0 1 2 3 ... 9 > > > > Output: > > > > 80 81 82 ... 89 > > > > > > > > With the new design, pin order is changed as follows: > > > > Input: > > > > 0 2 4 6 ... 18(ngpios * 2 - 2) > > > > Output: > > > > 1 3 5 7 ... 19(ngpios * 2 - 1) > > > > * Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by > > > > ast2600-sgpiom. > > > > * Fix coding style issues. > > > > > > > > Changes from v4: > > > > * Remove ngpios from dtsi > > > > * Add ast2400 and ast2500 platform data. > > > > * Remove unused macros. > > > > * Add ngpios check in a separate patch. > > > > * Fix coding style issues. > > > > > > > > Changes from v3: > > > > * Split dt-bindings patch to 2 patches > > > > * Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128 > > > > * Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80 > > > > * Correct the typo in commit messages. > > > > * Fix coding style issues. > > > > * Replace all of_*() APIs with device_*(). > > > > > > > > Changes from v2: > > > > * Remove maximum/minimum of ngpios from bindings. > > > > * Remove max-ngpios from bindings and dtsi. > > > > * Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and > > > > driver. > > > > * Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max > > > > number of available gpio pins are different. > > > > * Modify functions to pass aspeed_sgpio struct instead of passing > > > > max_ngpios. > > > > * Split sgpio driver patch to 3 patches > > > > > > > > Changes from v1: > > > > * Fix yaml format issues. > > > > * Fix issues reported by kernel test robot. > > > > > > > > Please help to review. > > > > > > > > Thanks, > > > > Steven > > > > > > > > Steven Lee (9): > > > > dt-bindings: aspeed-sgpio: Convert txt bindings to yaml. > > > > dt-bindings: aspeed-sgpio: Add ast2600 sgpio > > > > ARM: dts: aspeed-g6: Add SGPIO node. > > > > ARM: dts: aspeed-g5: Remove ngpios from sgpio node. > > > > gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support > > > > gpio: gpio-aspeed-sgpio: Add set_config function > > > > gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct > > > > gpio: gpio-aspeed-sgpio: Use generic device property APIs > > > > gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8. > > > > > > > > .../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++ > > > > .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ----- > > > > arch/arm/boot/dts/aspeed-g5.dtsi | 1 - > > > > arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++ > > > > drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++------- > > > > 5 files changed, 215 insertions(+), 115 deletions(-) > > > > create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml > > > > delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt > > > > > > > > -- > > > > 2.17.1 > > > > > > > > > > The series looks good to me. Can the DTS and GPIO patches go into > > > v5.15 separately? > > > > > > > Hi Bart, > > > > Thanks for the review. > > Shall we do anything to make the patches go into v5.15 or wait for picking-up? > > > > Steven > > > > > Bart > > It's more of a question to the relevant SoC maintainers. > > Joel, Andrew: can I take the GPIO patches through the GPIO tree and > you'll take the ARM patches separately into v5.15? I think that should be okay. I'll poke Joel. Andrew
On Tue, Aug 3, 2021 at 7:58 AM Joel Stanley <joel@jms.id.au> wrote: > > On Tue, 3 Aug 2021 at 04:49, Andrew Jeffery <andrew@aj.id.au> wrote: > > On Fri, 23 Jul 2021, at 17:00, Bartosz Golaszewski wrote: > > > Joel, Andrew: can I take the GPIO patches through the GPIO tree and > > > you'll take the ARM patches separately into v5.15? > > > > I think that should be okay. I'll poke Joel. > > Yes, that's fine. I have merged the first four patches into the aspeed tree. > > Cheers, > > Joel Thanks, I applied patches 5-9 to the GPIO tree. Bart
AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that supports up to 80 pins. In the current driver design, the max number of sgpio pins is hardcoded in macro MAX_NR_HW_SGPIO and the value is 80. For supporting sgpio master interfaces of AST2600 SoC, the patch series contains the following enhancement: - Convert txt dt-bindings to yaml. - Update aspeed-g6 dtsi to support the enhanced sgpio. - Support muiltiple SGPIO master interfaces. - Support up to 128 pins by dts ngpios property. - Pair input/output GPIOs instead of using 0 as GPIO input pin base and MAX_NR_HW_SGPIO as GPIO output pin base. - Support wdt reset tolerance. - Fix irq_chip issues which causes multiple sgpio devices use the same irq_chip data. - Replace all of_*() APIs with device_*(). Changes from v5: * Squash v5 patch-05 and patch-06 to one patch. * Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio input/output pin base are determined by ngpios. For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original pin order is as follows: Input: 0 1 2 3 ... 9 Output: 80 81 82 ... 89 With the new design, pin order is changed as follows: Input: 0 2 4 6 ... 18(ngpios * 2 - 2) Output: 1 3 5 7 ... 19(ngpios * 2 - 1) * Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by ast2600-sgpiom. * Fix coding style issues. Changes from v4: * Remove ngpios from dtsi * Add ast2400 and ast2500 platform data. * Remove unused macros. * Add ngpios check in a separate patch. * Fix coding style issues. Changes from v3: * Split dt-bindings patch to 2 patches * Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128 * Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80 * Correct the typo in commit messages. * Fix coding style issues. * Replace all of_*() APIs with device_*(). Changes from v2: * Remove maximum/minimum of ngpios from bindings. * Remove max-ngpios from bindings and dtsi. * Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and driver. * Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max number of available gpio pins are different. * Modify functions to pass aspeed_sgpio struct instead of passing max_ngpios. * Split sgpio driver patch to 3 patches Changes from v1: * Fix yaml format issues. * Fix issues reported by kernel test robot. Please help to review. Thanks, Steven Steven Lee (9): dt-bindings: aspeed-sgpio: Convert txt bindings to yaml. dt-bindings: aspeed-sgpio: Add ast2600 sgpio ARM: dts: aspeed-g6: Add SGPIO node. ARM: dts: aspeed-g5: Remove ngpios from sgpio node. gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support gpio: gpio-aspeed-sgpio: Add set_config function gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct gpio: gpio-aspeed-sgpio: Use generic device property APIs gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8. .../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++ .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ----- arch/arm/boot/dts/aspeed-g5.dtsi | 1 - arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++ drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++------- 5 files changed, 215 insertions(+), 115 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt -- 2.17.1