| Message ID | 20211218141024.500952-1-dmitry.baryshkov@linaro.org |
|---|---|
| Headers | show |
| Series | qcom: add support for PCIe on SM8450 platform | expand |
On Tue, 21 Dec 2021 at 22:52, Rob Herring <robh@kernel.org> wrote: > > On Tue, Dec 21, 2021 at 06:43:31PM +0300, Dmitry Baryshkov wrote: > > On Tue, 21 Dec 2021 at 17:59, Rob Herring <robh@kernel.org> wrote: > > > > > > On Sat, Dec 18, 2021 at 05:10:20PM +0300, Dmitry Baryshkov wrote: > > > > Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar > > > > to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use > > > > different set of clocks, so two compatible entries are required. > > > > > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > > > --- > > > > .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++++++++++++++++- > > > > 1 file changed, 21 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > > > > index a0ae024c2d0c..0adb56d5645e 100644 > > > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt > > > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > > > > @@ -15,6 +15,8 @@ > > > > - "qcom,pcie-sc8180x" for sc8180x > > > > - "qcom,pcie-sdm845" for sdm845 > > > > - "qcom,pcie-sm8250" for sm8250 > > > > + - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 > > > > + - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 > > > > > > What's the difference between the two? > > > > Clocks used by these hosts. Quoting the definition: > > > > + - "aggre0" Aggre NoC PCIe0 AXI clock, only > > for sm8450-pcie0 > > + - "aggre1" Aggre NoC PCIe1 AXI clock > > > > aggre1 is used by both pcie0 and pcie1, while aggre0 is used only by pcie0. > > That doesn't really seem like you need a different compatible for that. > Do you need to handle them differently? It seems like abuse of clocks > putting bus/interconnect clocks here, but sadly that's all too common. Unfortunately, yes, it looks like we need to handle them differently. The clocks are not handled by the interconnect on their own.
On Sat, 18 Dec 2021 17:10:20 +0300, Dmitry Baryshkov wrote: > Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar > to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use > different set of clocks, so two compatible entries are required. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++++++++++++++++- > 1 file changed, 21 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring <robh@kernel.org>
On Sat, Dec 18, 2021 at 05:10:19PM +0300, Dmitry Baryshkov wrote: > There are two different PCIe controllers and PHYs on SM8450, one having > one lane and another with two lanes. Add support for both PCIe > controllers > > Dependencies: > - https://lore.kernel.org/linux-arm-msm/20211218140223.500390-1-dmitry.baryshkov@linaro.org/ > > Changes since v4: > - Add PCIe1 support > - Change binding accordingly, to use qcom,pcie-sm8450-pcie0 and > qcom,pcie-sm8450-pcie1 compatibility strings > - Rebase on top of (pending) pipe_clock cleanup/rework patchset > > Changes since v3: > - Fix pcie gpios to follow defined schema as noted by Rob > - Fix commit message according to Bjorn's suggestions > > Changes since v2: > - Remove unnecessary comment in struct qcom_pcie_cfg > > Changes since v1: > - Fix capitalization/wording of PCI patch subjects > - Add missing gen3x1 specification to PHY table names > > ---------------------------------------------------------------- > Dmitry Baryshkov (5): > dt-bindings: pci: qcom: Document PCIe bindings for SM8450 > PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg > PCI: qcom: Add ddrss_sf_tbu flag > PCI: qcom: Add interconnect support to 2.7.0/1.9.0 ops > PCI: qcom: Add SM8450 PCIe support > > .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++- > drivers/pci/controller/dwc/pcie-qcom.c | 101 ++++++++++++++------- > 2 files changed, 91 insertions(+), 32 deletions(-) Need an ACK from pci-qcom maintainers, thanks. Lorenzo
On Sat 18 Dec 06:10 PST 2021, Dmitry Baryshkov wrote: > Qualcomm PCIe driver uses compatible string to check if the ddrss_sf_tbu > clock should be used. Since sc7280 support has added flags, switch to > the new mechanism to check if this clock should be used. > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 1204011c96ee..d8d400423a0a 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -191,6 +191,7 @@ struct qcom_pcie_ops { > struct qcom_pcie_cfg { > const struct qcom_pcie_ops *ops; > unsigned int pipe_clk_need_muxing:1; > + unsigned int has_ddrss_sf_tbu_clk:1; > }; > > struct qcom_pcie { > @@ -1133,7 +1134,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) > res->clks[3].id = "bus_slave"; > res->clks[4].id = "slave_q2a"; > res->clks[5].id = "tbu"; > - if (of_device_is_compatible(dev->of_node, "qcom,pcie-sm8250")) { > + if (pcie->cfg->has_ddrss_sf_tbu_clk) { > res->clks[6].id = "ddrss_sf_tbu"; > res->num_clks = 7; > } else { > @@ -1449,6 +1450,7 @@ static const struct qcom_pcie_cfg sdm845_cfg = { > > static const struct qcom_pcie_cfg sm8250_cfg = { > .ops = &ops_1_9_0, > + .has_ddrss_sf_tbu_clk = true, > }; > > static const struct qcom_pcie_cfg sc7280_cfg = { > -- > 2.34.1 >
On Sat 18 Dec 06:10 PST 2021, Dmitry Baryshkov wrote: > Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar > to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use > different set of clocks, so two compatible entries are required. > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++++++++++++++++- > 1 file changed, 21 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > index a0ae024c2d0c..0adb56d5645e 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > @@ -15,6 +15,8 @@ > - "qcom,pcie-sc8180x" for sc8180x > - "qcom,pcie-sdm845" for sdm845 > - "qcom,pcie-sm8250" for sm8250 > + - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 > + - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 > - "qcom,pcie-ipq6018" for ipq6018 > > - reg: > @@ -169,6 +171,24 @@ > - "ddrss_sf_tbu" PCIe SF TBU clock > - "pipe" PIPE clock > > +- clock-names: > + Usage: required for sm8450-pcie0 and sm8450-pcie1 > + Value type: <stringlist> > + Definition: Should contain the following entries > + - "aux" Auxiliary clock > + - "cfg" Configuration clock > + - "bus_master" Master AXI clock > + - "bus_slave" Slave AXI clock > + - "slave_q2a" Slave Q2A clock > + - "tbu" PCIe TBU clock > + - "ddrss_sf_tbu" PCIe SF TBU clock > + - "pipe" PIPE clock > + - "pipe_mux" PIPE MUX > + - "phy_pipe" PIPE output clock > + - "ref" REFERENCE clock > + - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0 > + - "aggre1" Aggre NoC PCIe1 AXI clock > + > - resets: > Usage: required > Value type: <prop-encoded-array> > @@ -246,7 +266,7 @@ > - "ahb" AHB reset > > - reset-names: > - Usage: required for sc8180x, sdm845 and sm8250 > + Usage: required for sc8180x, sdm845, sm8250 and sm8450 > Value type: <stringlist> > Definition: Should contain the following entries > - "pci" PCIe core reset > -- > 2.34.1 >
There are two different PCIe controllers and PHYs on SM8450, one having one lane and another with two lanes. Add support for both PCIe controllers Dependencies: - https://lore.kernel.org/linux-arm-msm/20211218140223.500390-1-dmitry.baryshkov@linaro.org/ Changes since v4: - Add PCIe1 support - Change binding accordingly, to use qcom,pcie-sm8450-pcie0 and qcom,pcie-sm8450-pcie1 compatibility strings - Rebase on top of (pending) pipe_clock cleanup/rework patchset Changes since v3: - Fix pcie gpios to follow defined schema as noted by Rob - Fix commit message according to Bjorn's suggestions Changes since v2: - Remove unnecessary comment in struct qcom_pcie_cfg Changes since v1: - Fix capitalization/wording of PCI patch subjects - Add missing gen3x1 specification to PHY table names ---------------------------------------------------------------- Dmitry Baryshkov (5): dt-bindings: pci: qcom: Document PCIe bindings for SM8450 PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg PCI: qcom: Add ddrss_sf_tbu flag PCI: qcom: Add interconnect support to 2.7.0/1.9.0 ops PCI: qcom: Add SM8450 PCIe support .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++- drivers/pci/controller/dwc/pcie-qcom.c | 101 ++++++++++++++------- 2 files changed, 91 insertions(+), 32 deletions(-)