| Message ID | 20220522155046.260146-1-tmaimon77@gmail.com |
|---|---|
| Headers | show |
| Series | Introduce Nuvoton Arbel NPCM8XX BMC SoC | expand |
On Sun, 22 May 2022, Tomer Maimon wrote: > Nuvoton Arbel BMC NPCM7XX contains an integrated clock controller, which > generates and supplies clocks to all modules within the BMC. > > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> > +static struct clk_hw * > +npcm8xx_clk_register_pll(void __iomem *pllcon, const char *name, > + const char *parent_name, unsigned long flags) > +{ > + struct npcm8xx_clk_pll *pll; > + struct clk_init_data init; > + struct clk_hw *hw; > + int ret; > + > + pll = kzalloc(sizeof(*pll), GFP_KERNEL); > + if (!pll) > + return ERR_PTR(-ENOMEM); > + > + pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name); > + > + init.name = name; > + init.ops = &npcm8xx_clk_pll_ops; > + init.parent_names = &parent_name; > + init.num_parents = 1; > + init.flags = flags; > + > + pll->pllcon = pllcon; > + pll->hw.init = &init; > + > + hw = &pll->hw; > + > + ret = clk_hw_register(NULL, hw); > + if (ret) { > + kfree(pll); > + hw = ERR_PTR(ret); > + } > + > + return hw; > +} > + > +#define NPCM8XX_CLKEN1 (0x00) > +#define NPCM8XX_CLKEN2 (0x28) > +#define NPCM8XX_CLKEN3 (0x30) > +#define NPCM8XX_CLKEN4 (0x70) > +#define NPCM8XX_CLKSEL (0x04) > +#define NPCM8XX_CLKDIV1 (0x08) > +#define NPCM8XX_CLKDIV2 (0x2C) > +#define NPCM8XX_CLKDIV3 (0x58) > +#define NPCM8XX_CLKDIV4 (0x7C) > +#define NPCM8XX_PLLCON0 (0x0C) > +#define NPCM8XX_PLLCON1 (0x10) > +#define NPCM8XX_PLLCON2 (0x54) > +#define NPCM8XX_SWRSTR (0x14) > +#define NPCM8XX_IRQWAKECON (0x18) > +#define NPCM8XX_IRQWAKEFLAG (0x1C) > +#define NPCM8XX_IPSRST1 (0x20) > +#define NPCM8XX_IPSRST2 (0x24) > +#define NPCM8XX_IPSRST3 (0x34) > +#define NPCM8XX_WD0RCR (0x38) > +#define NPCM8XX_WD1RCR (0x3C) > +#define NPCM8XX_WD2RCR (0x40) > +#define NPCM8XX_SWRSTC1 (0x44) > +#define NPCM8XX_SWRSTC2 (0x48) > +#define NPCM8XX_SWRSTC3 (0x4C) > +#define NPCM8XX_SWRSTC4 (0x50) > +#define NPCM8XX_CORSTC (0x5C) > +#define NPCM8XX_PLLCONG (0x60) > +#define NPCM8XX_AHBCKFI (0x64) > +#define NPCM8XX_SECCNT (0x68) > +#define NPCM8XX_CNTR25M (0x6C) > +#define NPCM8XX_THRTL_CNT (0xC0) > + > +struct npcm8xx_clk_gate_data { > + u32 reg; > + u8 bit_idx; > + const char *name; > + const char *parent_name; > + unsigned long flags; > + /* > + * If this clock is exported via DT, set onecell_idx to constant > + * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for > + * this specific clock. Otherwise, set to -1. > + */ > + int onecell_idx; > +}; > + > +struct npcm8xx_clk_mux_data { > + u8 shift; > + u8 mask; > + u32 *table; > + const char *name; > + const char * const *parent_names; > + u8 num_parents; > + unsigned long flags; > + /* > + * If this clock is exported via DT, set onecell_idx to constant > + * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for > + * this specific clock. Otherwise, set to -1. > + */ > + int onecell_idx; > + > +}; > + > +struct npcm8xx_clk_div_fixed_data { > + u8 mult; > + u8 div; > + const char *name; > + const char *parent_name; > + u8 clk_divider_flags; > + /* > + * If this clock is exported via DT, set onecell_idx to constant > + * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for > + * this specific clock. Otherwise, set to -1. > + */ > + int onecell_idx; > +}; > + > +struct npcm8xx_clk_div_data { > + u32 reg; > + u8 shift; > + u8 width; > + const char *name; > + const char *parent_name; > + u8 clk_divider_flags; > + unsigned long flags; > + /* > + * If this clock is exported via DT, set onecell_idx to constant > + * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for > + * this specific clock. Otherwise, set to -1. > + */ > + int onecell_idx; > +}; > + > +struct npcm8xx_clk_pll_data { > + u32 reg; > + const char *name; > + const char *parent_name; > + unsigned long flags; > + /* > + * If this clock is exported via DT, set onecell_idx to constant > + * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for > + * this specific clock. Otherwise, set to -1. > + */ > + int onecell_idx; > +}; > + > +/* > + * Single copy of strings used to refer to clocks within this driver indexed by > + * above enum. > + */ > +#define NPCM8XX_CLK_S_REFCLK "refclk" > +#define NPCM8XX_CLK_S_SYSBYPCK "sysbypck" > +#define NPCM8XX_CLK_S_MCBYPCK "mcbypck" > +#define NPCM8XX_CLK_S_GFXBYPCK "gfxbypck" > +#define NPCM8XX_CLK_S_PLL0 "pll0" > +#define NPCM8XX_CLK_S_PLL1 "pll1" > +#define NPCM8XX_CLK_S_PLL1_DIV2 "pll1_div2" > +#define NPCM8XX_CLK_S_PLL2 "pll2" > +#define NPCM8XX_CLK_S_PLL_GFX "pll_gfx" > +#define NPCM8XX_CLK_S_PLL2_DIV2 "pll2_div2" > +#define NPCM8XX_CLK_S_PIX_MUX "gfx_pixel" > +#define NPCM8XX_CLK_S_GPRFSEL_MUX "gprfsel_mux" > +#define NPCM8XX_CLK_S_MC_MUX "mc_phy" > +#define NPCM8XX_CLK_S_CPU_MUX "cpu" /*AKA system clock.*/ Add spaces around comment. > +#define NPCM8XX_CLK_S_MC "mc" > +#define NPCM8XX_CLK_S_AXI "axi" /*AKA CLK2*/ > +#define NPCM8XX_CLK_S_AHB "ahb" /*AKA CLK4*/ Ditto. > +static void __init npcm8xx_clk_init(struct device_node *clk_np) > +{ > + struct clk_hw_onecell_data *npcm8xx_clk_data; > + void __iomem *clk_base; > + struct resource res; > + struct clk_hw *hw; > + int ret; > + int i; > + > + ret = of_address_to_resource(clk_np, 0, &res); > + if (ret) { > + pr_err("%pOFn: failed to get resource, ret %d\n", clk_np, ret); > + return; > + } > + > + clk_base = ioremap(res.start, resource_size(&res)); > + if (!clk_base) > + goto npcm8xx_init_error; > + > + npcm8xx_clk_data = kzalloc(struct_size(npcm8xx_clk_data, hws, > + NPCM8XX_NUM_CLOCKS), GFP_KERNEL); > + if (!npcm8xx_clk_data) > + goto npcm8xx_init_np_err; > + > + npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS; > + > + for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++) > + npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); > + > + /* Register plls */ > + for (i = 0; i < ARRAY_SIZE(npcm8xx_plls); i++) { > + const struct npcm8xx_clk_pll_data *pll_data = &npcm8xx_plls[i]; > + > + hw = npcm8xx_clk_register_pll(clk_base + pll_data->reg, > + pll_data->name, > + pll_data->parent_name, > + pll_data->flags); > + if (IS_ERR(hw)) { Who deregisters the already registered plls on error paths? You might want to consider devm_ variants in npcm8xx_clk_register_pll() to make the cleanup simpler. Please check the other error path rollbacks from this point onward too. > + pr_err("npcm8xx_clk: Can't register pll\n"); > + goto npcm8xx_init_fail; > + } > + > + if (pll_data->onecell_idx >= 0) > + npcm8xx_clk_data->hws[pll_data->onecell_idx] = hw; > + } > + > + /* Register fixed dividers */ > + hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL1_DIV2, > + NPCM8XX_CLK_S_PLL1, 0, 1, 2); > + if (IS_ERR(hw)) { > + pr_err("npcm8xx_clk: Can't register fixed div\n"); > + goto npcm8xx_init_fail; > + } > + > + hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL2_DIV2, > + NPCM8XX_CLK_S_PLL2, 0, 1, 2); > + if (IS_ERR(hw)) { > + pr_err("npcm8xx_clk: Can't register pll div2\n"); > + goto npcm8xx_init_fail; > + } > + > + hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PRE_CLK, > + NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2); > + if (IS_ERR(hw)) { > + pr_err("npcm8xx_clk: Can't register ckclk div2\n"); > + goto npcm8xx_init_fail; > + } > + > + hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_AXI, > + NPCM8XX_CLK_S_TH, 0, 1, 2); > + if (IS_ERR(hw)) { > + pr_err("npcm8xx_clk: Can't register axi div2\n"); > + goto npcm8xx_init_fail; > + } > + > + hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_ATB, > + NPCM8XX_CLK_S_AXI, 0, 1, 2); > + if (IS_ERR(hw)) { > + pr_err("npcm8xx_clk: Can't register atb div2\n"); > + goto npcm8xx_init_fail; > + } > + > + /* Register muxes */ > + for (i = 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) { > + const struct npcm8xx_clk_mux_data *mux_data = &npcm8xx_muxes[i]; > + > + hw = clk_hw_register_mux_table(NULL, mux_data->name, > + mux_data->parent_names, > + mux_data->num_parents, > + mux_data->flags, > + clk_base + NPCM8XX_CLKSEL, > + mux_data->shift, > + mux_data->mask, 0, > + mux_data->table, > + &npcm8xx_clk_lock); > + > + if (IS_ERR(hw)) { > + pr_err("npcm8xx_clk: Can't register mux\n"); > + goto npcm8xx_init_fail; > + } > + > + if (mux_data->onecell_idx >= 0) > + npcm8xx_clk_data->hws[mux_data->onecell_idx] = hw; > + } > + > + /* Register clock dividers specified in npcm8xx_divs */ > + for (i = 0; i < ARRAY_SIZE(npcm8xx_divs); i++) { > + const struct npcm8xx_clk_div_data *div_data = &npcm8xx_divs[i]; > + > + hw = clk_hw_register_divider(NULL, div_data->name, > + div_data->parent_name, > + div_data->flags, > + clk_base + div_data->reg, > + div_data->shift, div_data->width, > + div_data->clk_divider_flags, > + &npcm8xx_clk_lock); > + if (IS_ERR(hw)) { > + pr_err("npcm8xx_clk: Can't register div table\n"); > + goto npcm8xx_init_fail; > + } > + > + if (div_data->onecell_idx >= 0) > + npcm8xx_clk_data->hws[div_data->onecell_idx] = hw; > + } > + > + ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, > + npcm8xx_clk_data); > + if (ret) > + pr_err("failed to add DT provider: %d\n", ret); > + > + of_node_put(clk_np); > + > + return; > + > +npcm8xx_init_fail: > + kfree(npcm8xx_clk_data->hws); > +npcm8xx_init_np_err: > + iounmap(clk_base); > +npcm8xx_init_error: > + of_node_put(clk_np); > +} > + > +CLK_OF_DECLARE(npcm8xx_clk_init, "nuvoton,npcm845-clk", npcm8xx_clk_init); >
On 22/05/2022 17:50, Tomer Maimon wrote: > Nuvoton Arbel BMC NPCM7XX contains an integrated clock controller, which > generates and supplies clocks to all modules within the BMC. > > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> > --- > .../bindings/clock/nuvoton,npcm845-clk.yaml | 68 +++++++++++++++++++ > .../dt-bindings/clock/nuvoton,npcm8xx-clock.h | 50 ++++++++++++++ > 2 files changed, 118 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml > create mode 100644 include/dt-bindings/clock/nuvoton,npcm8xx-clock.h > > diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml > new file mode 100644 > index 000000000000..f305c7c7eaf0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml > @@ -0,0 +1,68 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Nuvoton NPCM8XX Clock Controller Binding > + > +maintainers: > + - Tomer Maimon <tmaimon77@gmail.com> > + > +description: | > + Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which > + generates and supplies clocks to all modules within the BMC. > + > +properties: > + compatible: > + enum: > + - nuvoton,npcm845-clk > + > + reg: > + maxItems: 1 > + > + clocks: > + description: > + specify the external clocks used by the NPCM8XX clock module. Skip description, it's obvious. > + items: > + - description: 25M reference clock > + - description: CPU reference clock > + - description: MC reference clock > + > + clock-names: > + description: > + specify the external clocks names used by the NPCM8XX clock module. Skip description, it's obvious. > + items: > + - const: refclk Just "ref" > + - const: sysbypck > + - const: mcbypck Is "ck" short for "clk"? If yes, then just skip the suffix. > + > + '#clock-cells': > + const: 1 > + description: > + See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full > + list of NPCM8XX clock IDs. > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + > +additionalProperties: false > + > +examples: > + # Clock Control Module node: > + - | > + No need for blank line. > + ahb { > + #address-cells = <2>; > + #size-cells = <2>; > + > + clk: clock-controller@f0801000 { > + compatible = "nuvoton,npcm845-clk"; > + reg = <0x0 0xf0801000 0x0 0x1000>; > + #clock-cells = <1>; > + }; > + }; > + > +... > diff --git a/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h > new file mode 100644 > index 000000000000..d76f606bf88b > --- /dev/null > +++ b/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h Filename - same as bindings, so nuvoton,npcm845-clk.h > @@ -0,0 +1,50 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ Dual license, same as bindings. > +/* > + * Nuvoton NPCM8xx Clock Generator binding > + * clock binding number for all clocks supportted by nuvoton,npcm8xx-clk > + * > + * Copyright (C) 2021 Nuvoton Technologies tomer.maimon@nuvoton.com > + * > + */ > + > +#ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H > +#define __DT_BINDINGS_CLOCK_NPCM8XX_H > + > +#define NPCM8XX_CLK_CPU 0 > +#define NPCM8XX_CLK_GFX_PIXEL 1 > +#define NPCM8XX_CLK_MC 2 > +#define NPCM8XX_CLK_ADC 3 > +#define NPCM8XX_CLK_AHB 4 > +#define NPCM8XX_CLK_TIMER 5 > +#define NPCM8XX_CLK_UART 6 > +#define NPCM8XX_CLK_UART2 7 > +#define NPCM8XX_CLK_MMC 8 > +#define NPCM8XX_CLK_SPI3 9 > +#define NPCM8XX_CLK_PCI 10 > +#define NPCM8XX_CLK_AXI 11 > +#define NPCM8XX_CLK_APB4 12 > +#define NPCM8XX_CLK_APB3 13 > +#define NPCM8XX_CLK_APB2 14 > +#define NPCM8XX_CLK_APB1 15 > +#define NPCM8XX_CLK_APB5 16 > +#define NPCM8XX_CLK_CLKOUT 17 > +#define NPCM8XX_CLK_GFX 18 > +#define NPCM8XX_CLK_SU 19 > +#define NPCM8XX_CLK_SU48 20 > +#define NPCM8XX_CLK_SDHC 21 > +#define NPCM8XX_CLK_SPI0 22 > +#define NPCM8XX_CLK_SPI1 23 > +#define NPCM8XX_CLK_SPIX 24 > +#define NPCM8XX_CLK_RG 25 > +#define NPCM8XX_CLK_RCP 26 > +#define NPCM8XX_CLK_PRE_ADC 27 > +#define NPCM8XX_CLK_ATB 28 > +#define NPCM8XX_CLK_PRE_CLK 29 > +#define NPCM8XX_CLK_TH 30 > +#define NPCM8XX_CLK_REFCLK 31 > +#define NPCM8XX_CLK_SYSBYPCK 32 > +#define NPCM8XX_CLK_MCBYPCK 33 > + > +#define NPCM8XX_NUM_CLOCKS (NPCM8XX_CLK_MCBYPCK + 1) > + > +#endif Best regards, Krzysztof
On 22/05/2022 17:50, Tomer Maimon wrote: > Add a compatible string for Nuvoton BMC NPCM845 > global control registers (GCR). > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Mon, May 23, 2022 at 1:59 PM Arnd Bergmann <arnd@arndb.de> wrote: > > On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote: > > > > This patchset adds initial support for the Nuvoton > > Arbel NPCM8XX Board Management controller (BMC) SoC family. > > > > The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC. > > The NPCM8XX computing subsystem comprises a quadcore ARM > > Cortex A35 ARM-V8 architecture. > > > > This patchset adds minimal architecture and drivers such as: > > Clocksource, Clock, Reset, and WD. > > > > Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX. > > > > This patchset was tested on the Arbel NPCM8XX evaluation board. > > Thanks for your submission. Please note a few things about the process here: > > - The merge window is currently open, which means a lo Something wrong with the script? > Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX. > > This patchset was tested on the Arbel NPCM8XX evaluation board. > > Tomer Maimon (19): > dt-bindings: timer: npcm: Add npcm845 compatible string > clocksource: timer-npcm7xx: Add NPCM845 timer support > dt-bindings: serial: 8250: Add npcm845 compatible string > tty: serial: 8250: Add NPCM845 UART support > dt-bindings: watchdog: npcm: Add npcm845 compatible string > watchdog: npcm_wdt: Add NPCM845 watchdog support > dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock > clk: npcm8xx: add clock controller > dt-bindings: reset: add syscon property > reset: npcm: using syscon instead of device data > dt-bindings: reset: npcm: Add support for NPCM8XX > reset: npcm: Add NPCM8XX support > dt-bindings: arm: npcm: Add maintainer > dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string > dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string > arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC > arm64: dts: nuvoton: Add initial NPCM8XX device tree > arm64: dts: nuvoton: Add initial NPCM845 EVB device tree > arm64: defconfig: Add Nuvoton NPCM family supportt of maintainers > won't be reviewing your patches at the moment. It may be better to wait > for the -rc1 to be out before sending out v2 > > - don't send your patches to soc@kernel.org unless you want me to pick > them up into the soc tree and they have been reviewed already. The series > is clearly still under review at the moment, and I expect it to go through > a few revisions first. > > - gmail marked your emails as possible spam for me. I don't know what > happened here, but you may want to look into this to ensure that > everybody receives it. > > Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX. > > This patchset was tested on the Arbel NPCM8XX evaluation board. > > Tomer Maimon (19): > dt-bindings: timer: npcm: Add npcm845 compatible string > clocksource: timer-npcm7xx: Add NPCM845 timer support > dt-bindings: serial: 8250: Add npcm845 compatible string > tty: serial: 8250: Add NPCM845 UART support > dt-bindings: watchdog: npcm: Add npcm845 compatible string > watchdog: npcm_wdt: Add NPCM845 watchdog support > dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock > clk: npcm8xx: add clock controller > dt-bindings: reset: add syscon property > reset: npcm: using syscon instead of device data > dt-bindings: reset: npcm: Add support for NPCM8XX > reset: npcm: Add NPCM8XX support > dt-bindings: arm: npcm: Add maintainer > dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string > dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string > arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC > arm64: dts: nuvoton: Add initial NPCM8XX device tree > arm64: dts: nuvoton: Add initial NPCM845 EVB device tree > arm64: defconfig: Add Nuvoton NPCM family support > > - For an initial platform submission, I can merge the > clk/clocksource/serial/reset drivers along with the platform if they > have an Ack from the subsystem maintainers. I would normally > not include the watchdog patch in this as it's not essential, but > I suppose that it's fine if you only do a oneline change and it > has an Ack. If you have other nonessential drivers that need changes, > best submit them separately though. > > Arnd
Hi Stephen, Thanks for your comments. The patch will modify according to your comments and will be sent in the next kernel revision 5.19.rc1 On Thu, 26 May 2022 at 22:24, Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Tomer Maimon (2022-05-22 08:50:34) > > diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml > > new file mode 100644 > > index 000000000000..f305c7c7eaf0 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml > > @@ -0,0 +1,68 @@ > [...] > > + > > +required: > > + - compatible > > + - reg > > + - "#clock-cells" > > Are clocks not required because sometimes the reference clk isn't > connected? require, will be fixed > > > + > > +additionalProperties: false > > + > > +examples: > > + # Clock Control Module node: > > + - | > > + > > + ahb { > > drop ahb node please. > > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + clk: clock-controller@f0801000 { > > Drop label 'clk' as well please. > > > + compatible = "nuvoton,npcm845-clk"; > > + reg = <0x0 0xf0801000 0x0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + }; > > + > > +... Best regards, Tomer