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PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(39860400002)(376002)(346002)(396003)(136003)(451199018)(40470700004)(36840700001)(46966006)(7636003)(82740400003)(47076005)(426003)(66574015)(2906002)(1076003)(83380400001)(8936002)(7416002)(36756003)(40480700001)(5660300002)(82310400005)(86362001)(36860700001)(40460700003)(966005)(2616005)(356005)(41300700001)(26005)(186003)(6666004)(7696005)(316002)(54906003)(478600001)(110136005)(107886003)(336012)(70586007)(70206006)(4326008)(8676002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2023 18:25:03.5929 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a56240f-a230-4069-7e5b-08db29706c94 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6129 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Krzysztof. Thank you for the ACK on the Memory patches [2-5 & 8]. Rebased the patch series on latest next and added two more patches for 'memory' in v3. Please review and ACK if fine. [Patch v3 10/11] memory: tegra: handle no BWMGR MRQ support in BPMP [Patch v3 11/11] memory: tegra186-emc: fix interconnect registration Hi All, Requesting for ACK on below remaining patches and please consider for merging in "6.4". - Thierry: "Memory Interconnect base support" patches are dependent on the bpmp patch. [Patch v3 1/9] firmware: tegra: add function to get BPMP data - Rafael & Viresh: For the CPUFREQ MC Client patches. [Patch v3 06/11] arm64: tegra: Add cpu OPP tables and interconnects property [Patch v3 07/11] cpufreq: tegra194: add OPP support and set bandwidth - Lorenzo, Bjorn & Krzysztof Wilczyński: For the PCIE MC client patch. [Patch v3 09/11] PCI: tegra194: add interconnect support in Tegra234 Thank you, Sumit Gupta ============ This patch series adds memory interconnect support for Tegra234 SoC. It is used to dynamically scale DRAM Frequency as per the bandwidth requests from different Memory Controller (MC) clients. MC Clients use ICC Framework's icc_set_bw() api to dynamically request for the DRAM bandwidth (BW). As per path, the request will be routed from MC to the EMC driver. MC driver passes the request info like the Client ID, type, and frequency request info to the BPMP-FW which will set the final DRAM freq considering all exisiting requests. MC and EMC are the ICC providers. Nodes in path for a request will be: Client[1-n] -> MC -> EMC -> EMEM/DRAM The patch series also adds interconnect support in below client drivers: 1) CPUFREQ driver for scaling bandwidth with CPU frequency. For that, added per cluster OPP table which will be used in the CPUFREQ driver by requesting the minimum BW respective to the given CPU frequency in the OPP table of given cluster. 2) PCIE driver to request BW required for different modes. --- v2[2] -> v3: - in 'patch 7', set 'icc_dram_bw_scaling' to false if set_opp call failed to avoid flooding of uart with 'Failed to set bw' messages. - added 'patch 10' to handle if the bpmp-fw is old and not support bwmgr mrq. - added 'patch 11' to fix interconnect registration in tegra186-emc. ref patch link in linux next: [https://lore.kernel.org/all/20230306075651.2449-21-johan+linaro@kernel.org/] v1[1] -> v2: - moved BW setting to tegra234_mc_icc_set() from EMC driver. - moved sw clients to the 'tegra_mc_clients' table. - point 'node->data' to the entry within 'tegra_mc_clients'. - removed 'struct tegra_icc_node' and get client info using 'node->data'. - changed error handling in and around tegra_emc_interconnect_init(). - moved 'tegra-icc.h' from 'include/soc/tegra' to 'include/linux'. - added interconnect support to PCIE driver in 'Patch 9'. - merged 'Patch 9 & 10' from [1] to get num_channels and use. - merged 'Patch 2 & 3' from [1] to add ISO and NISO clients. - added 'Acked-by' of Krzysztof from 'Patch 05/10' of [1]. - Removed 'Patch 7' from [1] as that is merged now. Sumit Gupta (11): firmware: tegra: add function to get BPMP data memory: tegra: add interconnect support for DRAM scaling in Tegra234 memory: tegra: add mc clients for Tegra234 memory: tegra: add software mc clients in Tegra234 dt-bindings: tegra: add icc ids for dummy MC clients arm64: tegra: Add cpu OPP tables and interconnects property cpufreq: tegra194: add OPP support and set bandwidth memory: tegra: make cpu cluster bw request a multiple of mc channels PCI: tegra194: add interconnect support in Tegra234 memory: tegra: handle no BWMGR MRQ support in BPMP memory: tegra186-emc: fix interconnect registration race arch/arm64/boot/dts/nvidia/tegra234.dtsi | 276 ++++++++++ drivers/cpufreq/tegra194-cpufreq.c | 156 +++++- drivers/firmware/tegra/bpmp.c | 38 ++ drivers/memory/tegra/mc.c | 24 + drivers/memory/tegra/mc.h | 1 + drivers/memory/tegra/tegra186-emc.c | 118 ++++ drivers/memory/tegra/tegra234.c | 599 ++++++++++++++++++++- drivers/pci/controller/dwc/pcie-tegra194.c | 40 +- include/dt-bindings/memory/tegra234-mc.h | 5 + include/linux/tegra-icc.h | 65 +++ include/soc/tegra/bpmp.h | 5 + include/soc/tegra/mc.h | 8 +- 12 files changed, 1312 insertions(+), 23 deletions(-) create mode 100644 include/linux/tegra-icc.h [1] https://lore.kernel.org/lkml/20221220160240.27494-1-sumitg@nvidia.com/T/ [2] https://lore.kernel.org/linux-tegra/20230220140559.28289-1-sumitg@nvidia.com/