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[v8,00/10] ARM: stm32: add support for Phycore STM32MP1

Message ID 20230411083045.2850138-1-s.trumtrar@pengutronix.de
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Series ARM: stm32: add support for Phycore STM32MP1 | expand

Message

Steffen Trumtrar April 11, 2023, 8:30 a.m. UTC 
Hi,

this is the eighth installement of my series for adding support for the
Phytec STM32MP1-based SoM and board.

Phytec itself calls the board "Phycore STM32MP1-3" and has other
endnumbers. I only have access to the "-3" and that's what this series
adds.

    Changes since v7:
      - remove unused gpu_reservde memory range
      - get rid of duplicate ethernet clock assignments
      - remove secure-status for sdmmc
    
    Changes since v6:
      - rename mdio0->mdio

    Changes since v5:
      - add reviewed/acked-by
      - cleanup dt_bindings_check warnings

    Changes since v4:
      - cleanup usage of "status = okay|disabled"
      - fix remaining non-generic node names
      - rework sai nodes to not duplicate the existing settings in stm32mp151.dtsi

    Changes since v3:
      - cleanup board-compatible
      - cleanup aliases
      - rename nodes according to schema
      - use interrupt flag

Steffen Trumtrar (10):
  ARM: dts: stm32: Add alternate pinmux for ethernet
  ARM: dts: stm32: Add alternate pinmux for sai2b
  ARM: dts: stm32: Add new pinmux for sdmmc1_b4
  ARM: dts: stm32: Add new pinmux for sdmmc2_d47
  ARM: dts: stm32: Add pinmux for USART1 pins
  ARM: dts: stm32: Add idle/sleep pinmux for USART3
  ARM: dts: stm32: Add sleep pinmux for SPI1 pins_a
  dt-bindings: arm: stm32: Add Phytec STM32MP1 board
  ARM: dts: stm32: add STM32MP1-based Phytec SoM
  ARM: dts: stm32: add STM32MP1-based Phytec board

 .../devicetree/bindings/arm/stm32/stm32.yaml  |   6 +
 arch/arm/boot/dts/Makefile                    |   3 +-
 arch/arm/boot/dts/stm32mp15-pinctrl.dtsi      | 231 +++++++
 .../dts/stm32mp157c-phycore-stm32mp1-3.dts    |  60 ++
 .../stm32mp157c-phycore-stm32mp15-som.dtsi    | 577 ++++++++++++++++++
 5 files changed, 876 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts
 create mode 100644 arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi

Comments

Steffen Trumtrar May 2, 2023, 11:02 a.m. UTC | #1 
On 2023-04-11 at 10:30 +02, Steffen Trumtrar <s.trumtrar@pengutronix.de> wrote:

> Hi,
>
> this is the eighth installement of my series for adding support for the
> Phytec STM32MP1-based SoM and board.
>
> Phytec itself calls the board "Phycore STM32MP1-3" and has other
> endnumbers. I only have access to the "-3" and that's what this series
> adds.
>
>     Changes since v7:
>       - remove unused gpu_reservde memory range
>       - get rid of duplicate ethernet clock assignments
>       - remove secure-status for sdmmc
>
>     Changes since v6:
>       - rename mdio0->mdio
>
>     Changes since v5:
>       - add reviewed/acked-by
>       - cleanup dt_bindings_check warnings
>
>     Changes since v4:
>       - cleanup usage of "status = okay|disabled"
>       - fix remaining non-generic node names
>       - rework sai nodes to not duplicate the existing settings in stm32mp151.dtsi
>
>     Changes since v3:
>       - cleanup board-compatible
>       - cleanup aliases
>       - rename nodes according to schema
>       - use interrupt flag
>
> Steffen Trumtrar (10):
>   ARM: dts: stm32: Add alternate pinmux for ethernet
>   ARM: dts: stm32: Add alternate pinmux for sai2b
>   ARM: dts: stm32: Add new pinmux for sdmmc1_b4
>   ARM: dts: stm32: Add new pinmux for sdmmc2_d47
>   ARM: dts: stm32: Add pinmux for USART1 pins
>   ARM: dts: stm32: Add idle/sleep pinmux for USART3
>   ARM: dts: stm32: Add sleep pinmux for SPI1 pins_a
>   dt-bindings: arm: stm32: Add Phytec STM32MP1 board
>   ARM: dts: stm32: add STM32MP1-based Phytec SoM
>   ARM: dts: stm32: add STM32MP1-based Phytec board
>
>  .../devicetree/bindings/arm/stm32/stm32.yaml  |   6 +
>  arch/arm/boot/dts/Makefile                    |   3 +-
>  arch/arm/boot/dts/stm32mp15-pinctrl.dtsi      | 231 +++++++
>  .../dts/stm32mp157c-phycore-stm32mp1-3.dts    |  60 ++
>  .../stm32mp157c-phycore-stm32mp15-som.dtsi    | 577 ++++++++++++++++++
>  5 files changed, 876 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts
>  create mode 100644 arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi

Gentle ping. Anything I need to fix?

Best regards,
Steffen

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Alexandre TORGUE May 2, 2023, 3:20 p.m. UTC | #2 
Hi Steffen

On 4/11/23 10:30, Steffen Trumtrar wrote:
> Add another option for the ethernet0 pins.
> It is almost identical to ethernet0_rgmii_pins_c apart from TXD0/1.
> 
> This is used on the Phycore STM32MP1.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
>   arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 50 ++++++++++++++++++++++++
>   1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> index a9d2bec990141..1c97db4dbfc6d 100644
> --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> @@ -341,6 +341,56 @@ pins1 {
>   		};
>   	};
>   
> +	ethernet0_rgmii_pins_d: rgmii-3 {
> +		pins1 {
> +			pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
> +				 <STM32_PINMUX('G', 13, AF11)>,	/* ETH_RGMII_TXD0 */
> +				 <STM32_PINMUX('G', 14, AF11)>,	/* ETH_RGMII_TXD1 */
> +				 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
> +				 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
> +				 <STM32_PINMUX('B', 11, AF11)>,	/* ETH_RGMII_TX_CTL */
> +				 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
> +			bias-disable;
> +			drive-push-pull;
> +			slew-rate = <2>;
> +		};
> +		pins2 {
> +			pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
> +			bias-disable;
> +			drive-push-pull;
> +			slew-rate = <0>;
> +		};
> +		pins3 {
> +			pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
> +				 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
> +				 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
> +				 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
> +				 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
> +				 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
> +			bias-disable;
> +		};
> +	};
> +
> +	ethernet0_rgmii_sleep_pins_d: rgmii-sleep-8 {

Mistake here, it should be rgmii-sleep-3

> +		pins1 {
> +			pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
> +				 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
> +				 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
> +				 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
> +				 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
> +				 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
> +				 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
> +				 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
> +				 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
> +				 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
> +				 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
> +				 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
> +				 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
> +				 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
> +				 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
> +		};
> +	};
> +
>   	ethernet0_rmii_pins_a: rmii-0 {
>   		pins1 {
>   			pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */