From patchwork Mon Apr 17 06:50:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Tu X-Patchwork-Id: 674817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F157C77B70 for ; Mon, 17 Apr 2023 06:51:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229830AbjDQGvj (ORCPT ); Mon, 17 Apr 2023 02:51:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230257AbjDQGve (ORCPT ); Mon, 17 Apr 2023 02:51:34 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD3C51BB; Sun, 16 Apr 2023 23:50:44 -0700 (PDT) Received: from droid06.amlogic.com (10.18.11.248) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Mon, 17 Apr 2023 14:52:00 +0800 From: Yu Tu To: , , , , , Rob Herring , "Neil Armstrong" , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , "Krzysztof Kozlowski" , Martin Blumenstingl CC: , , Yu Tu Subject: [PATCH V7 0/4] Add S4 SoC PLL and Peripheral clock controller Date: Mon, 17 Apr 2023 14:50:01 +0800 Message-ID: <20230417065005.24967-1-yu.tu@amlogic.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 X-Originating-IP: [10.18.11.248] Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 1. Add S4 SoC PLL and Peripheral clock controller dt-bindings. 2. Add PLL and Peripheral clock controller driver for S4 SOC. Yu Tu (4): dt-bindings: clock: document Amlogic S4 SoC PLL clock controller dt-bindings: clock: document Amlogic S4 SoC peripherals clock controller clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver clk: meson: s4: add support for Amlogic S4 SoC peripheral clock controller V6 -> V7: Change send patch series as well change format and clock flags suggested by Jerome. Change dt-bindings suggested by Krzysztof. V5 -> V6: Change send patch series, as well change format and clock flags. V4 -> V5: change format and clock flags and adjust the patch series as suggested by Jerome. V3 -> V4: change format and clock flags. V2 -> V3: Use two clock controller. V1 -> V2: Change format as discussed in the email. Link:https://lore.kernel.org/all/20230116074214.2326-1-yu.tu@amlogic.com/ .../clock/amlogic,s4-peripherals-clkc.yaml | 97 + .../bindings/clock/amlogic,s4-pll-clkc.yaml | 50 + MAINTAINERS | 1 + drivers/clk/meson/Kconfig | 25 + drivers/clk/meson/Makefile | 2 + drivers/clk/meson/s4-peripherals.c | 3814 +++++++++++++++++ drivers/clk/meson/s4-peripherals.h | 217 + drivers/clk/meson/s4-pll.c | 902 ++++ drivers/clk/meson/s4-pll.h | 87 + .../clock/amlogic,s4-peripherals-clkc.h | 131 + .../dt-bindings/clock/amlogic,s4-pll-clkc.h | 30 + 11 files changed, 5356 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-peripherals-clkc.yaml create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml create mode 100644 drivers/clk/meson/s4-peripherals.c create mode 100644 drivers/clk/meson/s4-peripherals.h create mode 100644 drivers/clk/meson/s4-pll.c create mode 100644 drivers/clk/meson/s4-pll.h create mode 100644 include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h create mode 100644 include/dt-bindings/clock/amlogic,s4-pll-clkc.h base-commit: 5883d6b83cb0c84c8bc86bd1ff937ea313eb7325