From patchwork Wed May 24 13:01:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alexis_Lothor=C3=A9?= X-Patchwork-Id: 685447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90264C77B73 for ; Wed, 24 May 2023 13:01:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232079AbjEXNBT (ORCPT ); Wed, 24 May 2023 09:01:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229588AbjEXNBS (ORCPT ); Wed, 24 May 2023 09:01:18 -0400 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 085E699; Wed, 24 May 2023 06:01:13 -0700 (PDT) Received: (Authenticated sender: alexis.lothore@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 57DF56000F; Wed, 24 May 2023 13:01:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1684933272; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=OMEX7EeIbeQcBJX8PAIK5KbOxg0Lv8Wk2X1l3ikoIiw=; b=a9vrG/SKv93eJ0gFSpdGL/IsE3MIJeT5XdyfH9NU+C8RebTABfj+FPUQPHzm4FnVr9OLJR WNCIAAzbK/MmrVLkqelfWyG6DfbemeKTKgcSL4uE2zArogthBKDtlaJEFTTYCOTPJQsJvZ 99eQTVLzXYdKH81yMpZBrqthmDUh0Z/aErOVQKnBEIeYqOdH6H74wfoubFsBdgmLu9RFI1 bjjfgv9IvzB995bAm4XYmJ17RBCVaWAh/jvhlKOl0vtjs4ADxmqpgB+9oC1IV9KSZ5H12f SrTmet1d7v2xPniVlckaevNluXUMpAJgVXr34Do2qEYOxIuf5kPwojNZHjxDNw== From: =?utf-8?q?Alexis_Lothor=C3=A9?= To: Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, Thomas Petazzoni , paul.arola@telus.com, scott.roberts@telus.com, =?utf-8?q?Marek_Beh=C3=BAn?= , =?utf-8?q?Alexis_Lothor?= =?utf-8?q?=C3=A9?= Subject: [PATCH net-next v3 0/7] net: dsa: mv88e6xxx: add 88E6361 support Date: Wed, 24 May 2023 15:01:20 +0200 Message-Id: <20230524130127.268201-1-alexis.lothore@bootlin.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This series brings initial support for Marvell 88E6361 switch. MV88E6361 is a 8 ports switch with 5 integrated Gigabit PHYs and 3 2.5Gigabit SerDes interfaces. It is in fact a new variant in the 88E639X/88E6193X/88E6191X family with a subset of existing features: - port 0: MII, RMII, RGMII, 1000BaseX, 2500BaseX - port 3 to 7: triple speed internal phys - port 9 and 10: 1000BaseX, 25000BaseX Since said family is already well supported in mv88e6xxx driver, adding initial support for this new switch mostly consists in finding the ID exposed in its identification register, adding a proper description in switch description tables in mv88e6xxx driver, and enforcing 88E6361 specificities in mv88e6393x_XXX methods. - first 4 commits introduce an internal phy offset field for switches which have internal phys but not starting from port 0 - 5th commit is a fix on existing switches based on first commits - 6th commit is a slight modification to prepare 886361 support - last commit introduces 88E6361 support in 88E6393X family This initial support has been tested with two samples of a custom board with the following hardware configuration: - a main CPU connected to MV88E6361 using port 0 as CPU port - port 9 wired to a SFP cage - port 10 wired to a G.Hn transceiver The following setup was used: PC <-ethernet-> (copper SFP) - Board 1 - (G.hn) <-phone line(RJ11)-> (G.hn) Board 2 The unit 1 has been configured to bridge SFP port and G.hn port together, which allowed to successfully ping Board 2 from PC. Changes since v2: - add Reviewed-By tags for untouched patches - remove whitespace - reorganized some conditions to avoid weird line split Changes since v1: - rework mv88e6xxx_port_ppu_updates to use internal helper - add internal phys offset field to manage switches which do not have internal PHYs right on first ports - fix 88E639X/88E6193X/88E6191X internal phy layout - enforce 88E6361 features in mv88e6393x_port_set_speed_duplex - enforce 88E6361 features in mv88e6393x_port_max_speed_mode - enforce 88E6361 features in mv88e6393x_phylink_get_caps - add Reviewed-By and Acked-By on untouched patch Alexis Lothoré (7): dt-bindings: net: dsa: marvell: add MV88E6361 switch to compatibility list net: dsa: mv88e6xxx: pass directly chip structure to mv88e6xxx_phy_is_internal net: dsa: mv88e6xxx: use mv88e6xxx_phy_is_internal in mv88e6xxx_port_ppu_updates net: dsa: mv88e6xxx: add field to specify internal phys layout net: dsa: mv88e6xxx: fix 88E6393X family internal phys layout net: dsa: mv88e6xxx: pass mv88e6xxx_chip structure to port_max_speed_mode net: dsa: mv88e6xxx: enable support for 88E6361 switch .../devicetree/bindings/net/dsa/marvell.txt | 2 +- drivers/net/dsa/mv88e6xxx/chip.c | 69 ++++++++++++++----- drivers/net/dsa/mv88e6xxx/chip.h | 11 ++- drivers/net/dsa/mv88e6xxx/global2.c | 5 +- drivers/net/dsa/mv88e6xxx/port.c | 26 +++++-- drivers/net/dsa/mv88e6xxx/port.h | 13 ++-- 6 files changed, 94 insertions(+), 32 deletions(-)