| Message ID | 20230601093744.1565802-1-u-kumar1@ti.com |
|---|---|
| Headers | show |
| Series | arm64: dts: ti: k3-j7200: Add properties and sync with uboot | expand |
* Udit Kumar <u-kumar1@ti.com> [230601 09:38]: > There are timer IO pads in the MCU domain, and in the MAIN domain. These > pads can be muxed for the related timers. > > There are timer IO control registers for input and output. The registers > for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control > the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and > CTRLMMR_MCU_TIMERIO*_CTRL the output. > > The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control > Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the > CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview". > > For chaining timers, the timer IO control registers also have a CASCADE_EN > input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit > muxes the previous timer output, or possibly and external TIMER_IO pad > source, to the input clock of the selected timer instance for odd numered > timers. For the even numbered timers, the CASCADE_EN bit does not do > anything. The timer cascade input routing options are shown in TRM > "Figure 12-3224. Timers Overview". For handling beyond multiplexing, the > driver support for timer cascading should be likely be handled via the > clock framework. > > The MCU timer controls are also marked as reserved for > usage by the MCU firmware. Reviewed-by: Tony Lindgren <tony@atomide.com>
In continuation of patch series posted by Nishanth for sync of uboot device tree with kernel device tree for AM64 SOC. https://lore.kernel.org/linux-arm-kernel/20230414073328.381336-1-nm@ti.com/ This series extend device tree sync/clean up for J7200 SOC. This patch series build on top of https://lore.kernel.org/all/20230419040007.3022780-1-u-kumar1@ti.com Changes since v1: https://lore.kernel.org/all/20230426103219.1565266-1-u-kumar1@ti.com/ * Add general purpose timers: Addded CLKSEL_VD clock for odd numbered timers Marked MCU_Timer as reserved, fixed clock index for main_timer13 *Configure pinctrl for timer IO pads Marked mcu_timerio_input as reserved *main_pmx0 clean up Splitted into two patches, One for UART and second for i2c duplication removal *Add uart pin mux in wkup_pmx0 No change *Add bootph-pre-ram for u-boot patch dropped, later will add bootph-pre-ram property later for all nodes. Udit Kumar (5): arm64: dts: ti: k3-j7200: Add general purpose timers arm64: dts: ti: k3-j7200: Configure pinctrl for timer IO pads arm64: dts: ti: k3-j7200-common-proc-board: main_pmx0 clean up arm64: dts: ti: k3-j7200-common-proc-board: remove duplicate main_i2c0 pin mux arm64: dts: ti: k3-j7200-common-proc-board: Add uart pin mux in wkup_pmx0 .../dts/ti/k3-j7200-common-proc-board.dts | 32 ++- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 258 ++++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 150 ++++++++++ 3 files changed, 436 insertions(+), 4 deletions(-)