| Message ID | 20230703-topic-8250_qup_icc-v1-0-fea39aa07525@linaro.org |
|---|---|
| Headers | show |
| Series | Add interconnects to QUPs on SM8250 | expand |
On 03/07/2023 15:31, Konrad Dybcio wrote: > Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path. > Allow such case. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > .../devicetree/bindings/spi/qcom,spi-geni-qcom.yaml | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 03/07/2023 16:31, Konrad Dybcio wrote: > Describe the interconnect paths related to QUPs and add the power-domains > powering them. > > This is required for icc sync_state, as otherwise QUP access is gated. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 150 +++++++++++++++++++++++++++++++++++ > 1 file changed, 150 insertions(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 03/07/2023 15:31, Konrad Dybcio wrote: > Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path. > Allow such case. > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Mon, Jul 03, 2023 at 03:31:09PM +0200, Konrad Dybcio wrote: > SM8250 (like SM8150 but unlike all other QUP-equipped SoCs) doesn't > provide a qup-core path. Adjust the bindings and drivers as necessary, > and then describe the icc paths in the device tree. This makes it possible > for interconnect sync_state succeed so long as you don't use UFS. > The "qup-core" path is a vote between two nodes on the QUP0 BCM, to provide a frequency vote on the QUP core(s). Both SM8150 and SM8250 has this BCM, but as you point out it's not exposed through the interconnect provider. I don't know why this is, but I think it would be preferable to amend the provider. Regards, Bjorn > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > Konrad Dybcio (5): > dt-bindings: spi: spi-geni-qcom: Allow no qup-core icc path > dt-bindings: serial: geni-qcom: Allow no qup-core icc path > dt-bindings: i2c: qcom,i2c-geni: Allow no qup-core icc path > soc: qcom: geni-se: Allow any combination of icc paths > arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs > > .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 27 ++-- > .../bindings/serial/qcom,serial-geni-qcom.yaml | 26 ++-- > .../bindings/spi/qcom,spi-geni-qcom.yaml | 15 ++- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 150 +++++++++++++++++++++ > drivers/soc/qcom/qcom-geni-se.c | 9 +- > 5 files changed, 204 insertions(+), 23 deletions(-) > --- > base-commit: 296d53d8f84ce50ffaee7d575487058c8d437335 > change-id: 20230703-topic-8250_qup_icc-61768a34c7ec > > Best regards, > -- > Konrad Dybcio <konrad.dybcio@linaro.org> >
SM8250 (like SM8150 but unlike all other QUP-equipped SoCs) doesn't provide a qup-core path. Adjust the bindings and drivers as necessary, and then describe the icc paths in the device tree. This makes it possible for interconnect sync_state succeed so long as you don't use UFS. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- Konrad Dybcio (5): dt-bindings: spi: spi-geni-qcom: Allow no qup-core icc path dt-bindings: serial: geni-qcom: Allow no qup-core icc path dt-bindings: i2c: qcom,i2c-geni: Allow no qup-core icc path soc: qcom: geni-se: Allow any combination of icc paths arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 27 ++-- .../bindings/serial/qcom,serial-geni-qcom.yaml | 26 ++-- .../bindings/spi/qcom,spi-geni-qcom.yaml | 15 ++- arch/arm64/boot/dts/qcom/sm8250.dtsi | 150 +++++++++++++++++++++ drivers/soc/qcom/qcom-geni-se.c | 9 +- 5 files changed, 204 insertions(+), 23 deletions(-) --- base-commit: 296d53d8f84ce50ffaee7d575487058c8d437335 change-id: 20230703-topic-8250_qup_icc-61768a34c7ec Best regards,