[v5,04/10] dt-bindings: riscv: Add T-HEAD C920 compatibles

Message ID	0783d4e9c9fcea8a84a8a7245f87168d4b698149.1696663037.git.unicorn_wang@outlook.com
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Headers	show Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D81F11C82 for <devicetree@vger.kernel.org>; Sat, 7 Oct 2023 07:55:36 +0000 (UTC) From: Chen Wang <unicornxw@gmail.com> To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang <unicorn_wang@outlook.com>, Conor Dooley <conor.dooley@microchip.com> Subject: [PATCH v5 04/10] dt-bindings: riscv: Add T-HEAD C920 compatibles Date: Sat, 7 Oct 2023 15:55:27 +0800 Message-Id: <0783d4e9c9fcea8a84a8a7245f87168d4b698149.1696663037.git.unicorn_wang@outlook.com> In-Reply-To: <cover.1696663037.git.unicorn_wang@outlook.com> References: <cover.1696663037.git.unicorn_wang@outlook.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add Milk-V Pioneer RISC-V board support \| expand [v5,00/10] Add Milk-V Pioneer RISC-V board support [v5,01/10] riscv: Add SOPHGO SOC family Kconfig support [v5,02/10] dt-bindings: vendor-prefixes: add milkv/sophgo [v5,03/10] dt-bindings: riscv: add sophgo sg2042 bindings [v5,04/10] dt-bindings: riscv: Add T-HEAD C920 compatibles [v5,05/10] dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC [v5,06/10] dt-bindings: timer: Add Sophgo sg2042 CLINT timer [v5,07/10] dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi [v5,08/10] riscv: dts: add initial Sophgo SG2042 SoC device tree [v5,09/10] riscv: dts: sophgo: add Milk-V Pioneer board device tree [v5,10/10] riscv: defconfig: enable SOPHGO SoC

Message ID

0783d4e9c9fcea8a84a8a7245f87168d4b698149.1696663037.git.unicorn_wang@outlook.com

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New

Headers

From: Chen Wang <unicornxw@gmail.com>
To: aou@eecs.berkeley.edu,
	chao.wei@sophgo.com,
	conor@kernel.org,
	devicetree@vger.kernel.org,
	guoren@kernel.org,
	jszhang@kernel.org,
	krzysztof.kozlowski+dt@linaro.org,
	linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	palmer@dabbelt.com,
	paul.walmsley@sifive.com,
	robh+dt@kernel.org,
	xiaoguang.xing@sophgo.com,
	apatel@ventanamicro.com
Cc: Chen Wang <unicorn_wang@outlook.com>,
	Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v5 04/10] dt-bindings: riscv: Add T-HEAD C920 compatibles
Date: Sat,  7 Oct 2023 15:55:27 +0800
Message-Id: 
 <0783d4e9c9fcea8a84a8a7245f87168d4b698149.1696663037.git.unicorn_wang@outlook.com>
In-Reply-To: <cover.1696663037.git.unicorn_wang@outlook.com>
References: <cover.1696663037.git.unicorn_wang@outlook.com>
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Series

Add Milk-V Pioneer RISC-V board support | expand

Commit Message

Chen Wang Oct. 7, 2023, 7:55 a.m. UTC

From: Chen Wang <unicorn_wang@outlook.com>

The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C920 core is used in the SOPHGO's SG2042 SoC.

Acked-by: Chao Wei <chao.wei@sophgo.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 38c0b5213736..185a0191bad6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@  properties:
               - sifive,u74-mc
               - thead,c906
               - thead,c910
+              - thead,c920
           - const: riscv
       - items:
           - enum:

[v5,04/10] dt-bindings: riscv: Add T-HEAD C920 compatibles

Commit Message

Patch