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[209.132.180.67]) by mx.google.com with ESMTP id g5-v6si521608plm.445.2018.09.12.02.54.30; Wed, 12 Sep 2018 02:54:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J7iNXgPx; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727796AbeILO6P (ORCPT + 6 others); Wed, 12 Sep 2018 10:58:15 -0400 Received: from mail-ed1-f67.google.com ([209.85.208.67]:34833 "EHLO mail-ed1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726836AbeILO6O (ORCPT ); Wed, 12 Sep 2018 10:58:14 -0400 Received: by mail-ed1-f67.google.com with SMTP id y20-v6so1275892edq.2 for ; Wed, 12 Sep 2018 02:54:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=riG+y2OQmTlvhmbDhsUEl+RI4V/hGhEUB0MS2rrQeBQ=; b=J7iNXgPxBSZ+pki5xkFgN0QR8tpRD4VGQACWhqUWNwi7rc+e0kureuFPWn+6dNadnw Gk8mV9fDNXq68e+GmyyOI1J/pAGAkSxokIpX33cahxTw07n8xjiU0hBVxu95NGfBefQc eK/B3u36f2wFA5kIQ6PwGQHuJqFwLVPFfi0OQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=riG+y2OQmTlvhmbDhsUEl+RI4V/hGhEUB0MS2rrQeBQ=; b=qzpBGxq5bcN9NU0Roh35VZB+cTJsYAMRV98nLyh+u6xbp56o2KSsWp0TND0YR7Jx/L MZ89oAF2n2ERhu85p2CnPhR3txAQ0o8fzLPESeK43YDES4Kd/mfLG/lp6/1rmQdY6dZq Nf7E0bAzoQkcbX3Y9QwQvIZQh8f+xPeXnABhmIl9idPyB2t5aBO08sFmUfa4SqeS6BFM Ae3hEEKrZK7GKLp2NUI4DCr8chYa9K5czeVy1HQOEJfYOTeS+kUU6dZJ3hS10uS9LoRH 18murgHlZ4EZPoMxxemWrorAFXeZyRpC1U51Ja4brBDCgW19LJsB9wPGTi3So3wAlsRR 1YmQ== X-Gm-Message-State: APzg51CVqVj/cFl0GIlYcOS6KfKwfJ67NvNMm0VSQHQUhW6J7vFr9Vod AquD4PZhI4sCr3qnv05JSS4Wog== X-Received: by 2002:a50:d90e:: with SMTP id t14-v6mr1766863edj.241.1536746066927; Wed, 12 Sep 2018 02:54:26 -0700 (PDT) Received: from localhost ([49.248.190.214]) by smtp.gmail.com with ESMTPSA id x22-v6sm397969edb.8.2018.09.12.02.54.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Sep 2018 02:54:26 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, David Brown , Rob Herring , Mark Rutland , linux-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 09/16] arm: dts: msm8974: thermal: split address space into two Date: Wed, 12 Sep 2018 15:22:54 +0530 Message-Id: <088724896f21d556ecf1e16a6c59c0e404444fa6.1536744310.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We've earlier added support to split the register address space into TM and SROT regions. Split up the regmap address space into two for msm8974 that has a similar register layout. Since tsens-common.c/init_common() currently only registers one address space, the order is important (TM before SROT). This is OK since the code doesn't really use the SROT functionality yet. Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke --- arch/arm/boot/dts/qcom-msm8974.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.17.1 Acked-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index d9019a49b292..56dbbf788d15 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -427,9 +427,10 @@ }; }; - tsens: thermal-sensor@fc4a8000 { + tsens: thermal-sensor@fc4a9000 { compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a8000 0x2000>; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; #thermal-sensor-cells = <1>;