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[209.132.180.67]) by mx.google.com with ESMTP id ht3si8055459pbb.185.2014.05.21.15.53.01; Wed, 21 May 2014 15:53:01 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753527AbaEUWwx (ORCPT + 27 others); Wed, 21 May 2014 18:52:53 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:50812 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752469AbaEUWwu (ORCPT ); Wed, 21 May 2014 18:52:50 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s4LMqWpj032655; Wed, 21 May 2014 17:52:32 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4LMqV6k026703; Wed, 21 May 2014 17:52:31 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Wed, 21 May 2014 17:52:31 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4LMqU0x019858; Wed, 21 May 2014 17:52:30 -0500 From: Murali Karicheri To: , , , , , CC: Murali Karicheri , Mohit Kumar , Pratyush Anand , Richard Zhu , Kishon Vijay Abraham I , Marek Vasut Subject: [RFC PATCH] pcie-designware: DT documentation update to clarify DT properties Date: Wed, 21 May 2014 18:52:29 -0400 Message-ID: <1400712749-6490-1-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: m-karicheri2@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Current documentation is not clear enough about the mandatory bindings to be present in the device node of a snps,dw-pcie compatible pcie controller. In some cases the property is not present in all drivers. For example pcie_bus is specified as a clock, but only one of the driver uses it. This patch attempts to make the documentation consistent with current implementation so that it is clear enough for anyone who develops a dw-pcie compatible pcie driver. CC: Mohit Kumar CC: Jingoo Han CC: Pratyush Anand CC: Richard Zhu CC: Kishon Vijay Abraham I CC: Marek Vasut Signed-off-by: Murali Karicheri --- .../devicetree/bindings/pci/designware-pcie.txt | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index d6fae13..8b9dc52 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -4,12 +4,14 @@ Required properties: - compatible: should contain "snps,dw-pcie" to identify the core, plus an identifier for the specific instance, such as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie". -- reg: base addresses and lengths of the pcie controller, - the phy controller, additional register for the phy controller. +- reg: base addresses and lengths of the pcie controller. + index 0 - base address and length of RC's config space. + index 1 and above: additional registers for the PCI controller + that are specific to an implementation. - interrupts: interrupt values for level interrupt, pulse interrupt, special interrupt. -- clocks: from common clock binding: handle to pci clock. -- clock-names: from common clock binding: should be "pcie" and "pcie_bus". +- clocks: from common clock binding: handle to list of pci clock. +- clock-names: from common clock binding: pci clock names: "pcie" - #address-cells: set to <3> - #size-cells: set to <2> - device_type: set to "pci"