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[209.132.180.67]) by mx.google.com with ESMTP id ag3si17147315pbc.61.2014.09.09.13.17.50 for ; Tue, 09 Sep 2014 13:17:51 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752528AbaIIURl (ORCPT + 27 others); Tue, 9 Sep 2014 16:17:41 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:52741 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752395AbaIIURc (ORCPT ); Tue, 9 Sep 2014 16:17:32 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s89KGulA014194; Tue, 9 Sep 2014 15:16:56 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s89KGuNZ021566; Tue, 9 Sep 2014 15:16:56 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Tue, 9 Sep 2014 15:16:55 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s89KGsvg010696; Tue, 9 Sep 2014 15:16:55 -0500 From: Murali Karicheri To: , , , , , , , , , CC: Murali Karicheri Subject: [PATCH v2 1/2] PCI: keystone: remove handle of PCI mode configuration Date: Tue, 9 Sep 2014 16:17:14 -0400 Message-ID: <1410293835-13050-1-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: m-karicheri2@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.180 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Keystone PCI hardware supports both RC and EP modes and devcfg register has bits to boot strap the device to either of these modes. It seems proper to add this functionality to the boot loader rather than in the driver as device will be operating in either mode, not both any time. Currently the driver supports only RC mode and hence register configuration in the driver is not needed and driver can assume this is a RC hardware. Also update the DT documentation accordingly. Signed-off-by: Murali Karicheri --- - Added this separate patch to remove pci mode handling .../devicetree/bindings/pci/pci-keystone.txt | 4 +--- drivers/pci/host/pci-keystone.c | 21 ++------------------ 2 files changed, 3 insertions(+), 22 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index ceb3e24..bedacf0 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -13,9 +13,7 @@ Required Properties:- compatibility: "ti,keystone-pcie" reg: index 1 is the base address and length of DW application registers. - index 2 is the base address and length of PCI mode configuration - register. - index 3 is the base address and length of PCI device ID register. + index 2 is the base address and length of PCI device ID register. pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1 diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c index ff8ed25..f1119eb 100644 --- a/drivers/pci/host/pci-keystone.c +++ b/drivers/pci/host/pci-keystone.c @@ -35,10 +35,6 @@ #define MAX_MSI_HOST_IRQS 8 #define MAX_LEGACY_HOST_IRQS 4 -/* RC mode settings masks */ -#define PCIE_RC_MODE BIT(2) -#define PCIE_MODE_MASK (BIT(1) | BIT(2)) - /* DEV_STAT_CTRL */ #define PCIE_CAP_BASE 0x70 @@ -355,7 +351,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) void __iomem *reg_p; struct phy *phy; int ret = 0; - u32 val; ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie), GFP_KERNEL); @@ -365,18 +360,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) } pp = &ks_pcie->pp; - /* index 2 is the devcfg register for RC mode settings */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 2); - reg_p = devm_ioremap_resource(dev, res); - if (IS_ERR(reg_p)) - return PTR_ERR(reg_p); - - /* enable RC mode in devcfg */ - val = readl(reg_p); - val &= ~PCIE_MODE_MASK; - val |= PCIE_RC_MODE; - writel(val, reg_p); - /* initialize SerDes Phy if present */ phy = devm_phy_get(dev, "pcie-phy"); if (!IS_ERR_OR_NULL(phy)) { @@ -385,8 +368,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return ret; } - /* index 3 is to read PCI DEVICE_ID */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 3); + /* index 2 is to read PCI DEVICE_ID */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); reg_p = devm_ioremap_resource(dev, res); if (IS_ERR(reg_p)) return PTR_ERR(reg_p);