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[209.132.180.67]) by mx.google.com with ESMTP id g16si4397583pdf.0.2015.03.04.00.49.47; Wed, 04 Mar 2015 00:49:47 -0800 (PST) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756006AbbCDItl (ORCPT + 5 others); Wed, 4 Mar 2015 03:49:41 -0500 Received: from mail-pd0-f169.google.com ([209.85.192.169]:37019 "EHLO mail-pd0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759347AbbCDItj (ORCPT ); Wed, 4 Mar 2015 03:49:39 -0500 Received: by pdbnh10 with SMTP id nh10so29900369pdb.4 for ; Wed, 04 Mar 2015 00:49:39 -0800 (PST) X-Received: by 10.68.69.34 with SMTP id b2mr5098817pbu.88.1425458979419; Wed, 04 Mar 2015 00:49:39 -0800 (PST) Received: from localhost.localdomain ([124.219.30.17]) by mx.google.com with ESMTPSA id n4sm3326384pdl.12.2015.03.04.00.49.32 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Mar 2015 00:49:38 -0800 (PST) From: "pi-cheng.chen" To: Viresh Kumar , Matthias Brugger , Rob Herring , "Rafael J. Wysocki" , Thomas Petazzoni Cc: Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Catalin Marinas , Will Deacon , "pi-cheng.chen" , "Joe.C" , Eddie Huang , Howard Chen , Ashwin Chaugule , Mike Turquette , fan.chen@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linaro-kernel@lists.linaro.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 1/4] cpufreq-dt: add clock domain and intermediate frequency support Date: Wed, 4 Mar 2015 16:49:13 +0800 Message-Id: <1425458956-20665-2-git-send-email-pi-cheng.chen@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1425458956-20665-1-git-send-email-pi-cheng.chen@linaro.org> References: <1425458956-20665-1-git-send-email-pi-cheng.chen@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: pi-cheng.chen@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In this patch, CPU clock/power domain information is added into the platform_data of cpufreq-dt so that cpufreq-dt driver could check with CPUs share clock/power. Also, intermediate frequency support is added in this version. Since the program flows of .target_index and .target_intermediate are quite similar, consolidate the flow as a new function to keep readibility. Signed-off-by: pi-cheng.chen --- drivers/cpufreq/cpufreq-dt.c | 68 +++++++++++++++++++++++++++++++++++++++----- include/linux/cpufreq-dt.h | 7 +++++ 2 files changed, 68 insertions(+), 7 deletions(-) diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c index bab67db..5948bdf 100644 --- a/drivers/cpufreq/cpufreq-dt.c +++ b/drivers/cpufreq/cpufreq-dt.c @@ -34,25 +34,37 @@ struct private_data { struct regulator *cpu_reg; struct thermal_cooling_device *cdev; unsigned int voltage_tolerance; /* in percentage */ + unsigned long intermediate_freq; }; -static int set_target(struct cpufreq_policy *policy, unsigned int index) +static unsigned int get_intermediate(struct cpufreq_policy *policy, + unsigned int index) +{ + struct private_data *priv = policy->driver_data; + struct cpufreq_frequency_table *freq_table; + unsigned long freq = clk_get_rate(policy->clk); + + freq_table = cpufreq_frequency_get_table(policy->cpu); + + if (freq == priv->intermediate_freq || + freq_table[index].frequency * 1000 == freq) + return 0; + + return priv->intermediate_freq; +} + +static int set_frequency(struct cpufreq_policy *policy, long freq_Hz) { struct dev_pm_opp *opp; - struct cpufreq_frequency_table *freq_table = policy->freq_table; struct clk *cpu_clk = policy->clk; struct private_data *priv = policy->driver_data; struct device *cpu_dev = priv->cpu_dev; struct regulator *cpu_reg = priv->cpu_reg; unsigned long volt = 0, volt_old = 0, tol = 0; unsigned int old_freq, new_freq; - long freq_Hz, freq_exact; + long freq_exact; int ret; - freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000); - if (freq_Hz <= 0) - freq_Hz = freq_table[index].frequency * 1000; - freq_exact = freq_Hz; new_freq = freq_Hz / 1000; old_freq = clk_get_rate(cpu_clk) / 1000; @@ -112,6 +124,29 @@ static int set_target(struct cpufreq_policy *policy, unsigned int index) return ret; } +static int target_intermediate(struct cpufreq_policy *policy, + unsigned int index) +{ + struct private_data *priv = policy->driver_data; + long freq_Hz; + + freq_Hz = priv->intermediate_freq; + return set_frequency(policy, freq_Hz); +} + +static int set_target(struct cpufreq_policy *policy, unsigned int index) +{ + struct cpufreq_frequency_table *freq_table = policy->freq_table; + struct clk *cpu_clk = policy->clk; + long freq_Hz; + + freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000); + if (freq_Hz <= 0) + freq_Hz = freq_table[index].frequency * 1000; + + return set_frequency(policy, freq_Hz); +} + static int allocate_resources(int cpu, struct device **cdev, struct regulator **creg, struct clk **cclk) { @@ -296,6 +331,23 @@ static int cpufreq_init(struct cpufreq_policy *policy) pd = cpufreq_get_driver_data(); if (!pd || !pd->independent_clocks) cpumask_setall(policy->cpus); + else if (pd && !list_empty(&pd->domain_list)) { + struct list_head *domain_node; + struct cpufreq_cpu_domain *domain; + + list_for_each(domain_node, &pd->domain_list) { + domain = container_of(domain_node, + struct cpufreq_cpu_domain, node); + if (!cpumask_test_cpu(policy->cpu, &domain->cpus)) + continue; + + if (domain->intermediate_freq) + priv->intermediate_freq = + domain->intermediate_freq; + cpumask_copy(policy->cpus, &domain->cpus); + break; + } + } of_node_put(np); @@ -363,6 +415,8 @@ static struct cpufreq_driver dt_cpufreq_driver = { .verify = cpufreq_generic_frequency_table_verify, .target_index = set_target, .get = cpufreq_generic_get, + .get_intermediate = get_intermediate, + .target_intermediate = target_intermediate, .init = cpufreq_init, .exit = cpufreq_exit, .ready = cpufreq_ready, diff --git a/include/linux/cpufreq-dt.h b/include/linux/cpufreq-dt.h index 0414009..d6e2097 100644 --- a/include/linux/cpufreq-dt.h +++ b/include/linux/cpufreq-dt.h @@ -10,6 +10,12 @@ #ifndef __CPUFREQ_DT_H__ #define __CPUFREQ_DT_H__ +struct cpufreq_cpu_domain { + struct list_head node; + cpumask_t cpus; + unsigned long intermediate_freq; +}; + struct cpufreq_dt_platform_data { /* * True when each CPU has its own clock to control its @@ -17,6 +23,7 @@ struct cpufreq_dt_platform_data { * clock. */ bool independent_clocks; + struct list_head domain_list; }; #endif /* __CPUFREQ_DT_H__ */