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[209.132.180.67]) by mx.google.com with ESMTP id bd12si3972752pdb.255.2015.03.04.00.50.24; Wed, 04 Mar 2015 00:50:25 -0800 (PST) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933854AbbCDIuJ (ORCPT + 28 others); Wed, 4 Mar 2015 03:50:09 -0500 Received: from mail-pa0-f43.google.com ([209.85.220.43]:46351 "EHLO mail-pa0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933788AbbCDIuG (ORCPT ); Wed, 4 Mar 2015 03:50:06 -0500 Received: by pabli10 with SMTP id li10so31731125pab.13 for ; Wed, 04 Mar 2015 00:50:05 -0800 (PST) X-Received: by 10.70.88.105 with SMTP id bf9mr4927139pdb.77.1425459005632; Wed, 04 Mar 2015 00:50:05 -0800 (PST) Received: from localhost.localdomain ([124.219.30.17]) by mx.google.com with ESMTPSA id n4sm3326384pdl.12.2015.03.04.00.49.57 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Mar 2015 00:50:04 -0800 (PST) From: "pi-cheng.chen" To: Viresh Kumar , Matthias Brugger , Rob Herring , "Rafael J. Wysocki" , Thomas Petazzoni Cc: Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Catalin Marinas , Will Deacon , "pi-cheng.chen" , "Joe.C" , Eddie Huang , Howard Chen , Ashwin Chaugule , Mike Turquette , fan.chen@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linaro-kernel@lists.linaro.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 4/4] ARM64: dts: mediatek: add cpufreq dts for MT8173 SoC Date: Wed, 4 Mar 2015 16:49:16 +0800 Message-Id: <1425458956-20665-5-git-send-email-pi-cheng.chen@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1425458956-20665-1-git-send-email-pi-cheng.chen@linaro.org> References: <1425458956-20665-1-git-send-email-pi-cheng.chen@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: pi-cheng.chen@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch illustrates how to enable mtk-cpufreq driver for a Mediatek SoC in device tree using MT8173 as an example. This patch was tested on MT8173 EVB with several patches which are not yet posted on public mailing list. Signed-off-by: pi-cheng.chen --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 10 ++++++++++ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 25 +++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index b57f095..cc3b954 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -417,3 +417,13 @@ status = "okay"; clock-frequency = <100000>; }; + +&cpu0 { + cpu-supply = <&mt6397_vpca15_reg>; + voltage-tolerance = <1>; +}; + +&cpu2 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index dd0a445..4ad75a6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -51,6 +51,16 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x000>; + clocks = <&infracfg INFRA_CA53SEL>; + operating-points = < + 1508000 1109000 + 1404000 1083000 + 1183000 1028000 + 1105000 1009000 + 1001000 983000 + 702000 908000 + 507000 859000 + >; }; cpu1: cpu@1 { @@ -65,6 +75,16 @@ compatible = "arm,cortex-a57"; reg = <0x100>; enable-method = "psci"; + clocks = <&infracfg INFRA_CA57SEL>; + operating-points = < + 1807000 1089000 + 1612000 1049000 + 1404000 1007000 + 1209000 968000 + 1001000 927000 + 702000 867000 + 507000 828000 + >; }; cpu3: cpu@101 { @@ -75,6 +95,11 @@ }; }; + cpufreq { + compatible = "mediatek,mtk-cpufreq"; + clocks = <&apmixedsys APMIXED_MAINPLL>; + }; + psci { compatible = "arm,psci"; method = "smc";