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[209.132.180.67]) by mx.google.com with ESMTP id gh2si8568717pbd.154.2015.07.09.03.28.19; Thu, 09 Jul 2015 03:28:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753090AbbGIK2M (ORCPT + 8 others); Thu, 9 Jul 2015 06:28:12 -0400 Received: from mail-pa0-f52.google.com ([209.85.220.52]:36427 "EHLO mail-pa0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753131AbbGIK16 (ORCPT ); Thu, 9 Jul 2015 06:27:58 -0400 Received: by pacgz10 with SMTP id gz10so75119784pac.3 for ; Thu, 09 Jul 2015 03:27:58 -0700 (PDT) X-Received: by 10.70.131.73 with SMTP id ok9mr29851496pdb.109.1436437678387; Thu, 09 Jul 2015 03:27:58 -0700 (PDT) Received: from localhost.localdomain ([124.219.30.17]) by smtp.googlemail.com with ESMTPSA id ju3sm5449083pbc.33.2015.07.09.03.27.55 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Jul 2015 03:27:57 -0700 (PDT) From: Pi-Cheng Chen To: Viresh Kumar , Michael Turquette , Matthias Brugger , Mark Rutland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linaro-kernel@lists.linaro.org, linux-mediatek@lists.infradead.org Subject: [PATCH v6 2/4] dt-bindings: mediatek: Add MT8173 cpufreq driver bindings Date: Thu, 9 Jul 2015 18:27:39 +0800 Message-Id: <1436437661-17606-3-git-send-email-pi-cheng.chen@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1436437661-17606-1-git-send-email-pi-cheng.chen@linaro.org> References: <1436437661-17606-1-git-send-email-pi-cheng.chen@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: pi-cheng.chen@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.52 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch adds device tree binding document for MT8173 cpufreq driver. The clock and regulator consumer properties are documented in Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt and referenced by this document. Signed-off-by: Pi-Cheng Chen --- .../devicetree/bindings/cpufreq/cpufreq-mt8173.txt | 134 +++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt new file mode 100644 index 0000000..f23873f --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt @@ -0,0 +1,134 @@ + +Mediatek MT8173 cpufreq driver +------------------------------ + +Mediatek MT8173 cpufreq driver for CPU frequency scaling. + +Please refer to Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt for details +about the regulator and clock consumer properties. + +Required properties: +- operating-points: Please refer to Documentation/devicetree/bindings/power/opp.txt for + details. + +Optional properties: +- #cooling-cells: +- cooling-min-level: +- cooling-max-level: + Please refer to Documentation/devicetree/bindings/thermal/thermal.txt. + +Example: +-------- + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x000>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points = < + 507000 859000 + 702000 908000 + 1001000 983000 + 1105000 1009000 + 1183000 1028000 + 1404000 1083000 + 1508000 1109000 + 1573000 1125000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x001>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points = < + 507000 859000 + 702000 908000 + 1001000 983000 + 1105000 1009000 + 1183000 1028000 + 1404000 1083000 + 1508000 1109000 + 1573000 1125000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA57SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points = < + 507000 828000 + 702000 867000 + 1001000 927000 + 1209000 968000 + 1404000 1007000 + 1612000 1049000 + 1807000 1089000 + 1989000 1125000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA57SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points = < + 507000 828000 + 702000 867000 + 1001000 927000 + 1209000 968000 + 1404000 1007000 + 1612000 1049000 + 1807000 1089000 + 1989000 1125000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; + }; + + &cpu0 { + proc-supply = <&mt6397_vpca15_reg>; + }; + + &cpu1 { + proc-supply = <&mt6397_vpca15_reg>; + }; + + &cpu2 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; + }; + + &cpu3 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; + };