From patchwork Thu Aug 27 12:34:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel Fernandez X-Patchwork-Id: 52766 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f197.google.com (mail-wi0-f197.google.com [209.85.212.197]) by patches.linaro.org (Postfix) with ESMTPS id 809B622DC4 for ; Thu, 27 Aug 2015 12:35:44 +0000 (UTC) Received: by wibcx1 with SMTP id cx1sf3024606wib.0 for ; Thu, 27 Aug 2015 05:35:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=7jtKN/RTHOQX0fnCuJA0neE0ZXJMxbwnWTx13DrbB4A=; b=ZA65+tJen51FY815kGFabFkHbhdTptQBbEY7vuEWoDwMqijGot/lw1lb/PSDdctpxw 1li565c+rjv4TaOq2x9jkh99wdlu9StYVmcK7soZTCCNTqV7lfZU5W5H1jiZQzBIpZqF FwGW3Q8wUkOS7jDcrj+wpyGPaU0IeKxRXtPIXf2XOqqiPNk83BLkDmnRI8hM5vFEnwu6 512yKQoxrn8jacOkoeRuaXP4ApYRuQC+tnOmlwUUtLEcvSXJaa4mb6zF8Hq0MPP/aThc XRqHYfslpGmEab4IY5iw124K3px1oOeh+z6qije5oC4GuhMzSZQ/f52s5PzmfuWzbLEt nWVg== X-Gm-Message-State: ALoCoQkuMWMc9YrR+NhhZSTSgP2gH1VwFI93OXYuAuFnY5cjc3ek75hbsTm6Tr/7mp/MGsO1JwCy X-Received: by 10.112.189.105 with SMTP id gh9mr1118511lbc.16.1440678943865; Thu, 27 Aug 2015 05:35:43 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.246.36 with SMTP id xt4ls94968lac.1.gmail; Thu, 27 Aug 2015 05:35:43 -0700 (PDT) X-Received: by 10.152.170.230 with SMTP id ap6mr2126421lac.73.1440678943563; Thu, 27 Aug 2015 05:35:43 -0700 (PDT) Received: from mail-lb0-f173.google.com (mail-lb0-f173.google.com. [209.85.217.173]) by mx.google.com with ESMTPS id f3si2049271lag.4.2015.08.27.05.35.43 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Aug 2015 05:35:43 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) client-ip=209.85.217.173; Received: by lbbtg9 with SMTP id tg9so10431077lbb.1 for ; Thu, 27 Aug 2015 05:35:43 -0700 (PDT) X-Received: by 10.152.164.130 with SMTP id yq2mr1787026lab.76.1440678943411; Thu, 27 Aug 2015 05:35:43 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.162.200 with SMTP id yc8csp4613490lbb; Thu, 27 Aug 2015 05:35:42 -0700 (PDT) X-Received: by 10.66.219.5 with SMTP id pk5mr6116733pac.111.1440678941270; Thu, 27 Aug 2015 05:35:41 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id zq10si3448903pbc.220.2015.08.27.05.35.40; Thu, 27 Aug 2015 05:35:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753809AbbH0Mfj (ORCPT + 28 others); Thu, 27 Aug 2015 08:35:39 -0400 Received: from mail-wi0-f180.google.com ([209.85.212.180]:36824 "EHLO mail-wi0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753760AbbH0Mef (ORCPT ); Thu, 27 Aug 2015 08:34:35 -0400 Received: by wicgk12 with SMTP id gk12so7209429wic.1 for ; Thu, 27 Aug 2015 05:34:34 -0700 (PDT) X-Received: by 10.194.47.209 with SMTP id f17mr4562324wjn.39.1440678874570; Thu, 27 Aug 2015 05:34:34 -0700 (PDT) Received: from lmenx315.st.com. ([80.12.39.94]) by smtp.gmail.com with ESMTPSA id ik8sm2925826wjb.8.2015.08.27.05.34.31 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Aug 2015 05:34:33 -0700 (PDT) From: Gabriel Fernandez To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , " David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo , Arnd Bergmann , Viresh Kumar , Thierry Reding , Phil Edworthy , Minghuan Lian , Tanmay Inamdar , , Sachin Kamat , Andrew Lunn , Liviu Dudau , Zhou Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, linux-pci@vger.kernel.org, Lee Jones Subject: [PATCH v4 2/4] PCI: st: Add Device Tree bindings for sti pcie Date: Thu, 27 Aug 2015 14:34:15 +0200 Message-Id: <1440678857-27118-3-git-send-email-gabriel.fernandez@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1440678857-27118-1-git-send-email-gabriel.fernandez@linaro.org> References: <1440678857-27118-1-git-send-email-gabriel.fernandez@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: gabriel.fernandez@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier Signed-off-by: Gabriel Fernandez --- Documentation/devicetree/bindings/pci/st-pcie.txt | 53 +++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt b/Documentation/devicetree/bindings/pci/st-pcie.txt new file mode 100644 index 0000000..25fcab3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st-pcie.txt @@ -0,0 +1,53 @@ +STMicroelectronics STi PCIe controller + +This PCIe host controller is based on the Synopsis Designware PCIe IP +and thus inherits all the common properties defined in designware-pcie.txt. + +Required properties: + - compatible: "st,stih407-pcie" + - reg: base address and length of the pcie controller, mem-window address + and length available to the controller. + - interrupts: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. + - interrupt-names: Should be "msi". STi interrupt that is asserted when an + MSI is received. + - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg + offset for IP configuration. + - resets, reset-names: the power-down and soft-reset lines of PCIe IP. + Associated names must be "powerdown" and "softreset". + - phys, phy-names: the phandle for the PHY device. + Associated name must be "pcie" + +Optional properties: + - reset-gpio: a GPIO spec to define which pin is connected to the bus reset. + +Example: + +pcie0: pcie@9b00000 { + compatible = "st,pcie", "snps,dw-pcie"; + device_type = "pci"; + reg = <0x09b00000 0x4000>, /* dbi cntrl registers */ + <0x2fff0000 0x00010000>, /* configuration space */ + <0x40000000 0x80000000>; /* lmi mem window */ + reg-names = "dbi", "config", "mem-window"; + st,syscfg = <&syscfg_core 0xd8 0xe0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x0FFF0000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /* INT A */ + <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* INT B */ + <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* INT C */ + <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /* INT D */ + + resets = <&powerdown STIH407_PCIE0_POWERDOWN>, + <&softreset STIH407_PCIE0_SOFTRESET>; + reset-names = "powerdown", + "softreset"; + phys = <&phy_port0 PHY_TYPE_PCIE>; + phy-names = "pcie"; +};