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[209.85.217.173]) by mx.google.com with ESMTPS id ei11si1565309lad.12.2015.09.30.18.20.00 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Sep 2015 18:20:00 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) client-ip=209.85.217.173; Received: by lbos8 with SMTP id s8so619984lbo.0 for ; Wed, 30 Sep 2015 18:20:00 -0700 (PDT) X-Received: by 10.112.199.70 with SMTP id ji6mr2036964lbc.73.1443662400171; Wed, 30 Sep 2015 18:20:00 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp286053lbq; Wed, 30 Sep 2015 18:19:58 -0700 (PDT) X-Received: by 10.50.57.102 with SMTP id h6mr379603igq.29.1443662398662; Wed, 30 Sep 2015 18:19:58 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 103si2806554iol.12.2015.09.30.18.19.58; Wed, 30 Sep 2015 18:19:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753328AbbJABT5 (ORCPT + 7 others); Wed, 30 Sep 2015 21:19:57 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:34761 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752189AbbJABT4 (ORCPT ); Wed, 30 Sep 2015 21:19:56 -0400 Received: by padhy16 with SMTP id hy16so56760478pad.1 for ; Wed, 30 Sep 2015 18:19:56 -0700 (PDT) X-Received: by 10.68.108.101 with SMTP id hj5mr8453544pbb.156.1443662396032; Wed, 30 Sep 2015 18:19:56 -0700 (PDT) Received: from localhost.localdomain ([173.14.250.228]) by smtp.gmail.com with ESMTPSA id ne10sm382861pbc.96.2015.09.30.18.19.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 Sep 2015 18:19:54 -0700 (PDT) From: Tyler Baker To: arm@kernel.org, Wei Xu Cc: grant.likely@linaro.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Will Deacon , Haojian Zhuang , Bintian Wang , Peter Griffin , Kevin Hilman , Mark Brown , Arnd Bergmann , Ricardo Salveti , Amit Kucheria , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tyler Baker Subject: [PATCH v2] arm64: dts: add all hi6220 uart nodes Date: Wed, 30 Sep 2015 18:19:48 -0700 Message-Id: <1443662388-25686-1-git-send-email-tyler.baker@linaro.org> X-Mailer: git-send-email 2.1.4 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: tyler.baker@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch adds all UART nodes for the Hi6220 SoC. Recently a board[1] has been developed to standardize UART access across all the 96boards consumer edition boards. To use this hardware on HiKey we must configure and enable UART3. However, to ensure backward compatibility we must keep UART0 enabled as well. I have removed the hard coded clock index values in favor of using the ones already defined in include/dt-bindings/clock/hi6220-clock.h. Since UART0 needs to be soldered, it has been suggested to use the UART3 as the default console. This patch was boot tested on top of next-20150930, with both UART configurations. [1] http://www.seeedstudio.com/depot/96Boards-UART-p-2525.html?ref=newInBazaar Signed-off-by: Tyler Baker --- In v2: - Drop unused alias, and add comments. (Arnd, Rob) - Switch default console to use UART3 with stdout-path. (Mark, Rob) arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 7 +++-- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 43 +++++++++++++++++++++++++- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index e36a539..aa101ac 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -17,11 +17,14 @@ compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; aliases { - serial0 = &uart0; + serial0 = &uart0; /* On board UART0 */ + serial1 = &uart1; /* BT UART */ + serial2 = &uart2; /* LS Expansion UART0 */ + serial3 = &uart3; /* LS Expansion UART1 */ }; chosen { - stdout-path = "serial0:115200n8"; + stdout-path = "serial3:115200n8"; }; memory@0 { diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 3f03380..82d2488 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -5,6 +5,7 @@ */ #include +#include / { compatible = "hisilicon,hi6220"; @@ -164,8 +165,48 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf8015000 0x0 0x1000>; interrupts = ; - clocks = <&ao_ctrl 36>, <&ao_ctrl 36>; + clocks = <&ao_ctrl HI6220_UART0_PCLK>, + <&ao_ctrl HI6220_UART0_PCLK>; clock-names = "uartclk", "apb_pclk"; }; + + uart1: uart@f7111000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf7111000 0x0 0x1000>; + interrupts = ; + clocks = <&sys_ctrl HI6220_UART1_PCLK>, + <&sys_ctrl HI6220_UART1_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: uart@f7112000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf7112000 0x0 0x1000>; + interrupts = ; + clocks = <&sys_ctrl HI6220_UART2_PCLK>, + <&sys_ctrl HI6220_UART2_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart3: uart@f7113000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf7113000 0x0 0x1000>; + interrupts = ; + clocks = <&sys_ctrl HI6220_UART3_PCLK>, + <&sys_ctrl HI6220_UART3_PCLK>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart4: uart@f7114000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf7114000 0x0 0x1000>; + interrupts = ; + clocks = <&sys_ctrl HI6220_UART4_PCLK>, + <&sys_ctrl HI6220_UART4_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; }; };