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[209.132.180.67]) by mx.google.com with ESMTP id bx2si7651193pab.140.2015.10.13.14.08.21; Tue, 13 Oct 2015 14:08:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932172AbbJMVIU (ORCPT + 7 others); Tue, 13 Oct 2015 17:08:20 -0400 Received: from mail-gw2-out.broadcom.com ([216.31.210.63]:18457 "EHLO mail-gw2-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932115AbbJMVIT (ORCPT ); Tue, 13 Oct 2015 17:08:19 -0400 X-IronPort-AV: E=Sophos;i="5.17,680,1437462000"; d="scan'208";a="77549795" Received: from irvexchcas06.broadcom.com (HELO IRVEXCHCAS06.corp.ad.broadcom.com) ([10.9.208.53]) by mail-gw2-out.broadcom.com with ESMTP; 13 Oct 2015 14:36:55 -0700 Received: from IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) by IRVEXCHCAS06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server (TLS) id 14.3.235.1; Tue, 13 Oct 2015 14:08:18 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) with Microsoft SMTP Server id 14.3.235.1; Tue, 13 Oct 2015 14:08:18 -0700 Received: from venom.rtp.broadcom.com (unknown [10.27.64.103]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id DDCDE40FEB; Tue, 13 Oct 2015 14:05:23 -0700 (PDT) From: Jon Mason To: Michael Turquette , Stephen Boyd CC: Florian Fainelli , Hauke Mehrtens , Ray Jui , Scott Branden , , , , , Subject: [PATCH v2 2/7] clk: iproc: Add PWRCTRL support Date: Tue, 13 Oct 2015 17:08:00 -0400 Message-ID: <1444770485-11210-3-git-send-email-jonmason@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444770485-11210-1-git-send-email-jonmason@broadcom.com> References: <1444770485-11210-1-git-send-email-jonmason@broadcom.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: jonmason@broadcom.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.174 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Some iProc SoC clocks use a different way to control clock power, via the PWRDWN bit in the PLL control register. Since the PLL control register is used to access the PWRDWN bit, there is no need for the pwr_base when this is being used. A new flag, IPROC_CLK_EMBED_PWRCTRL, has been added to identify this usage. We can use the AON interface to write the values to enable/disable PWRDOWN. Signed-off-by: Jon Mason --- drivers/clk/bcm/clk-iproc-pll.c | 55 ++++++++++++++++++++++++++++------------- drivers/clk/bcm/clk-iproc.h | 6 +++++ 2 files changed, 44 insertions(+), 17 deletions(-) diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c index 2dda4e8..e029ab3 100644 --- a/drivers/clk/bcm/clk-iproc-pll.c +++ b/drivers/clk/bcm/clk-iproc-pll.c @@ -148,14 +148,25 @@ static void __pll_disable(struct iproc_pll *pll) writel(val, pll->asiu_base + ctrl->asiu.offset); } - /* latch input value so core power can be shut down */ - val = readl(pll->pwr_base + ctrl->aon.offset); - val |= (1 << ctrl->aon.iso_shift); - writel(val, pll->pwr_base + ctrl->aon.offset); - - /* power down the core */ - val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); - writel(val, pll->pwr_base + ctrl->aon.offset); + if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { + val = readl(pll->pll_base + ctrl->aon.offset); + val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); + writel(val, pll->pll_base + ctrl->aon.offset); + + if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) + readl(pll->pll_base + ctrl->aon.offset); + } + + if (pll->pwr_base) { + /* latch input value so core power can be shut down */ + val = readl(pll->pwr_base + ctrl->aon.offset); + val |= (1 << ctrl->aon.iso_shift); + writel(val, pll->pwr_base + ctrl->aon.offset); + + /* power down the core */ + val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); + writel(val, pll->pwr_base + ctrl->aon.offset); + } } static int __pll_enable(struct iproc_pll *pll) @@ -163,11 +174,22 @@ static int __pll_enable(struct iproc_pll *pll) const struct iproc_pll_ctrl *ctrl = pll->ctrl; u32 val; - /* power up the PLL and make sure it's not latched */ - val = readl(pll->pwr_base + ctrl->aon.offset); - val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; - val &= ~(1 << ctrl->aon.iso_shift); - writel(val, pll->pwr_base + ctrl->aon.offset); + if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { + val = readl(pll->pll_base + ctrl->aon.offset); + val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); + writel(val, pll->pll_base + ctrl->aon.offset); + + if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) + readl(pll->pll_base + ctrl->aon.offset); + } + + if (pll->pwr_base) { + /* power up the PLL and make sure it's not latched */ + val = readl(pll->pwr_base + ctrl->aon.offset); + val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; + val &= ~(1 << ctrl->aon.iso_shift); + writel(val, pll->pwr_base + ctrl->aon.offset); + } /* certain PLLs also need to be ungated from the ASIU top level */ if (ctrl->flags & IPROC_CLK_PLL_ASIU) { @@ -610,9 +632,8 @@ void __init iproc_pll_clk_setup(struct device_node *node, if (WARN_ON(!pll->pll_base)) goto err_pll_iomap; + /* Some SoCs do not require the pwr_base, thus failing is not fatal */ pll->pwr_base = of_iomap(node, 1); - if (WARN_ON(!pll->pwr_base)) - goto err_pwr_iomap; /* some PLLs require gating control at the top ASIU level */ if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) { @@ -695,9 +716,9 @@ err_pll_register: iounmap(pll->asiu_base); err_asiu_iomap: - iounmap(pll->pwr_base); + if (pll->pwr_base) + iounmap(pll->pwr_base); -err_pwr_iomap: iounmap(pll->pll_base); err_pll_iomap: diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h index d834b7a..ff7bfad 100644 --- a/drivers/clk/bcm/clk-iproc.h +++ b/drivers/clk/bcm/clk-iproc.h @@ -49,6 +49,12 @@ #define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4) /* + * Some PLLs use a different way to control clock power, via the PWRDWN bit in + * the PLL control register + */ +#define IPROC_CLK_EMBED_PWRCTRL BIT(5) + +/* * Parameters for VCO frequency configuration * * VCO frequency =