From patchwork Mon Feb 22 14:01:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 62577 Delivered-To: patch@linaro.org Received: by 10.112.43.199 with SMTP id y7csp1252464lbl; Mon, 22 Feb 2016 06:01:11 -0800 (PST) X-Received: by 10.66.157.161 with SMTP id wn1mr38465513pab.146.1456149671772; Mon, 22 Feb 2016 06:01:11 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 70si39983770pfn.223.2016.02.22.06.01.11; Mon, 22 Feb 2016 06:01:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dkim=neutral (body hash did not verify) header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755098AbcBVOBK (ORCPT + 6 others); Mon, 22 Feb 2016 09:01:10 -0500 Received: from mail-lb0-f179.google.com ([209.85.217.179]:34650 "EHLO mail-lb0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755096AbcBVOBJ (ORCPT ); Mon, 22 Feb 2016 09:01:09 -0500 Received: by mail-lb0-f179.google.com with SMTP id of3so82309265lbc.1 for ; Mon, 22 Feb 2016 06:01:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=lEfSENWOgNUr32i1RZ/D29lCcZ3za3BSvYgHJja9fwU=; b=MA+SxCOn5pbW8D73+Mvws78CKSgThGPq4fLSMFoZSjXQnCt+mbp4XYNrfQEH6R8ac8 GegO/u77tIUOGjnZK13mmJWB1bZWNfAfTb4yqUuFDoNaeCpxdKo69ciHKJtaOW3vL+/w buoeMoVBiC5bOoo9Q//GX64M6VAjsl02OE3sA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=lEfSENWOgNUr32i1RZ/D29lCcZ3za3BSvYgHJja9fwU=; b=nC4DBbIvnqAJeh/TT89jqERa2XNY5ZOrnfIJ8VpHO7eWdpFKOTVkgUrUBUu+TWv3o4 tp91PrWV3XVwT3A/MznBKSEK1BfB3Rs3moNbE/gWHEwj4bbLqTJ8UvU6EMZWit9LMl0a XFefsP3HfCN4gPzh5cbyFzNOZ/OhdFZQlphV/X3YNxBX8UUV6Dbfql2SPtGNmH+LavtZ yIrrJsskZmj9NKTwhuWqLbPk4VuEKXI61nYRtHzNCYNuTzL21Hjk6h0HJQtyym19+2lA 9fQ5wXqeu//9J5NaG8araliKzdphWejDt011Pqxzaj6sO11kW3QVqPlYrNG2+tE1OvRf /BWg== X-Gm-Message-State: AG10YOSizyQxFI2VmxOzsLjKRyH/hbLrHPcjF4A7qBXdaTS4be4KuMA8PT7TvOx3t3sVQKB4 X-Received: by 10.112.159.10 with SMTP id wy10mr10280288lbb.114.1456149667306; Mon, 22 Feb 2016 06:01:07 -0800 (PST) Received: from localhost.localdomain ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id pi5sm3252885lbb.41.2016.02.22.06.01.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Feb 2016 06:01:06 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Marc Zyngier Cc: Pawel Moll , Mark Rutland , Will Deacon , Rob Herring , Russell King , Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 1/3 v2] irqchip: gic/realview: support more RealView DCC variants Date: Mon, 22 Feb 2016 15:01:01 +0100 Message-Id: <1456149661-19118-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the add-on file for the GIC dealing with the RealView family we currently only handle the PB11MPCore, let's extend this to manage the RealView EB ARM11MPCore as well. The Revision B of the ARM11MPCore core tile is a bit special and needs special handling as it moves a system control register around at random. Cc: Arnd Bergmann Cc: Marc Zyngier Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Detect syscon register location based on the syscon compatible string instead of the GIC compatible string, just define one compatible string for the 11mp test chip GIC. - Consistently return -ENODEV This can be applied in isolation from the other patches so Marc one you're happy with it, please take it into the IRQchip tree. --- .../bindings/interrupt-controller/arm,gic.txt | 1 + drivers/irqchip/irq-gic-realview.c | 44 +++++++++++++++++++--- 2 files changed, 39 insertions(+), 6 deletions(-) -- 2.4.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt index 5a1cb4bc3dfe..793c20ff8fcc 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt @@ -16,6 +16,7 @@ Main node required properties: "arm,cortex-a15-gic" "arm,cortex-a7-gic" "arm,cortex-a9-gic" + "arm,eb11mp-gic" "arm,gic-400" "arm,pl390" "arm,tc11mp-gic" diff --git a/drivers/irqchip/irq-gic-realview.c b/drivers/irqchip/irq-gic-realview.c index aa46eb280a7f..54c296401525 100644 --- a/drivers/irqchip/irq-gic-realview.c +++ b/drivers/irqchip/irq-gic-realview.c @@ -10,7 +10,8 @@ #include #define REALVIEW_SYS_LOCK_OFFSET 0x20 -#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74 +#define REALVIEW_SYS_PLD_CTRL1 0x74 +#define REALVIEW_EB_REVB_SYS_PLD_CTRL1 0xD8 #define VERSATILE_LOCK_VAL 0xA05F #define PLD_INTMODE_MASK BIT(22)|BIT(23)|BIT(24) #define PLD_INTMODE_LEGACY 0x0 @@ -18,26 +19,57 @@ #define PLD_INTMODE_NEW_NO_DCC BIT(23) #define PLD_INTMODE_FIQ_ENABLE BIT(24) +/* For some reason RealView EB Rev B moved this register */ +static const struct of_device_id syscon_pldset_of_match[] = { + { + .compatible = "arm,realview-eb11mp-revb-syscon", + .data = (void *)REALVIEW_EB_REVB_SYS_PLD_CTRL1, + }, + { + .compatible = "arm,realview-eb11mp-revc-syscon", + .data = (void *)REALVIEW_SYS_PLD_CTRL1, + }, + { + .compatible = "arm,realview-eb-syscon", + .data = (void *)REALVIEW_SYS_PLD_CTRL1, + }, + { + .compatible = "arm,realview-pb11mp-syscon", + .data = (void *)REALVIEW_SYS_PLD_CTRL1, + }, + {}, +}; + static int __init realview_gic_of_init(struct device_node *node, struct device_node *parent) { static struct regmap *map; + struct device_node *np; + const struct of_device_id *gic_id; + u32 pld1_ctrl; + + np = of_find_matching_node_and_match(NULL, syscon_pldset_of_match, + &gic_id); + if (!np) + return -ENODEV; + pld1_ctrl = (u32)gic_id->data; /* The PB11MPCore GIC needs to be configured in the syscon */ - map = syscon_regmap_lookup_by_compatible("arm,realview-pb11mp-syscon"); + map = syscon_node_to_regmap(np); if (!IS_ERR(map)) { /* new irq mode with no DCC */ regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, VERSATILE_LOCK_VAL); - regmap_update_bits(map, REALVIEW_PB11MP_SYS_PLD_CTRL1, + regmap_update_bits(map, pld1_ctrl, PLD_INTMODE_NEW_NO_DCC, PLD_INTMODE_MASK); regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 0x0000); - pr_info("TC11MP GIC: set up interrupt controller to NEW mode, no DCC\n"); + pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n"); } else { - pr_err("TC11MP GIC setup: could not find syscon\n"); - return -ENXIO; + pr_err("RealView GIC setup: could not find syscon\n"); + return -ENODEV; } return gic_of_init(node, parent); } IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init); +IRQCHIP_DECLARE(armeb11mp_gic, "arm,eb11mp-gic", realview_gic_of_init);