From patchwork Thu Jun 2 15:17:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 69188 Delivered-To: patch@linaro.org Received: by 10.140.106.246 with SMTP id e109csp173131qgf; Thu, 2 Jun 2016 08:18:32 -0700 (PDT) X-Received: by 10.98.37.5 with SMTP id l5mr5213476pfl.56.1464880712701; Thu, 02 Jun 2016 08:18:32 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g132si1025471pfc.38.2016.06.02.08.18.32; Thu, 02 Jun 2016 08:18:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932909AbcFBPSb (ORCPT + 7 others); Thu, 2 Jun 2016 11:18:31 -0400 Received: from arroyo.ext.ti.com ([198.47.19.12]:57246 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932892AbcFBPSb (ORCPT ); Thu, 2 Jun 2016 11:18:31 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u52FHje5031774; Thu, 2 Jun 2016 10:17:45 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u52FHjIa027659; Thu, 2 Jun 2016 10:17:45 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Thu, 2 Jun 2016 10:17:45 -0500 Received: from ula0868495.am.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u52FHi4c021497; Thu, 2 Jun 2016 10:17:45 -0500 From: Murali Karicheri To: , , , , , , , , , Subject: [PATCH v1 2/2] ARM: dts: keystone: add interrupt property to PCI controller bindings Date: Thu, 2 Jun 2016 11:17:52 -0400 Message-ID: <1464880672-15203-2-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464880672-15203-1-git-send-email-m-karicheri2@ti.com> References: <1464880672-15203-1-git-send-email-m-karicheri2@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now that Keystone PCIe controller supports error interrupt handling add interrupt property to PCI controller DT bindings to enable error interrupt handling. Signed-off-by: Murali Karicheri --- - v1 - no change from initial version - applies to master v4.7-rcx at kernel.org git repo arch/arm/boot/dts/keystone-k2e.dtsi | 2 ++ arch/arm/boot/dts/keystone.dtsi | 2 ++ 2 files changed, 4 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index 5374c9a..9a51b8c 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -104,6 +104,8 @@ num-lanes = <2>; bus-range = <0x00 0xff>; + /* error interrupt */ + interrupts = ; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index f627a1c..e23f46d 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -302,6 +302,8 @@ num-lanes = <2>; bus-range = <0x00 0xff>; + /* error interrupt */ + interrupts = ; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */