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[209.132.180.67]) by mx.google.com with ESMTP id 18si49935525pfk.163.2016.08.10.12.56.53; Wed, 10 Aug 2016 12:56:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934161AbcHJT4q (ORCPT + 7 others); Wed, 10 Aug 2016 15:56:46 -0400 Received: from mail-wm0-f43.google.com ([74.125.82.43]:34871 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935616AbcHJT4o (ORCPT ); Wed, 10 Aug 2016 15:56:44 -0400 Received: by mail-wm0-f43.google.com with SMTP id f65so109957988wmi.0 for ; Wed, 10 Aug 2016 12:56:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=Qc2eoVfwtUzV3DgWC9VJyjyJEu1HfCIJ7oKzufpagRA=; b=ZuLsOIH/RxCCVgBNB/zbzhYFiue8U7r6RucdQOwzUT+Y5S41K/LmQiB+9tkHCCWg64 9jXOE68zDJLXCOh0kg3Cc+KG8ySPq2gCWud+gd6VFfJTg/rlEhUpAlFdJZlXxrtdqvUz 1J3xQoaUw9u0AzsxNv5nnHYsAIxHt+p8NmQnw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Qc2eoVfwtUzV3DgWC9VJyjyJEu1HfCIJ7oKzufpagRA=; b=CVt3J4d5jUn24TrMOp90qojEuTgc2cAa8jz6fSFeW0LDiLGALbT4A6UEDfRJF/tx6K mn1hm9VzAUOhpJZ0pg8mVFwtfnJbGoNd7rt8fewbegxTFWDptMg0zIw49Jx8g2EoGB1l Gg7ZMiSk3KS+VcjHh0xM/t0lgl3QNT8TuNcDHbY/H1Rqb1Fpy5YKqg0o957xE/mF8sp/ Zw1fNNLj7CaYPbi2dx7Uwj2JMdVcUzff1+AfsNSLKEk8Dx5D0sQb8G8G8bm3QeGTCdsv SwlsljQR+b1mnhwvc9rjXweILsxGLLeY6ebzQK3J/6gQoHFLupAxKG4pQzsT28hzRjtX UU5A== X-Gm-Message-State: AEkoouuva12i/upV0Y1N2OinfwhjtltQCeSQLUmidx1P8kNWtENXawZqmgteksXbK+7G42lS X-Received: by 10.25.205.200 with SMTP id d191mr461562lfg.212.1470820183566; Wed, 10 Aug 2016 02:09:43 -0700 (PDT) Received: from linuslaptop.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id h22sm7417698lji.21.2016.08.10.02.09.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Aug 2016 02:09:42 -0700 (PDT) From: Linus Walleij To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, Linus Walleij , devicetree@vger.kernel.org, Russell King Subject: [PATCH 1/3] clk: versatile add DT bindings for the ICST CM variants Date: Wed, 10 Aug 2016 11:09:32 +0200 Message-Id: <1470820172-12840-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Integrator/AP and Integrator/CP core modules have special versions of the ICST525 interface hardcoding some bits. Create special compatible strings to identify these variants, also explain a bit what is going on. Cc: devicetree@vger.kernel.org Cc: Russell King Signed-off-by: Linus Walleij --- .../devicetree/bindings/clock/arm-syscon-icst.txt | 35 ++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt index 8b7177cecb36..48886490591a 100644 --- a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt +++ b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt @@ -5,20 +5,51 @@ Technology (IDT). ARM integrated these oscillators deeply into their reference designs by adding special control registers that manage such oscillators to their system controllers. -The ARM system controller contains logic to serialize and initialize +The ARM system controllers contains logic to serialize and initialize an ICST clock request after a write to the 32 bit register at an offset into the system controller. Furthermore, to even be able to alter one of these frequencies, the system controller must first be unlocked by writing a special token to another offset in the system controller. +The ARM Integrator/AP and Integrator/CP core modules and baseboard contain +special versions of the serial interface that only connects the low 8 bits +of the VDW (missing one bit), hardwires RDW to different values and sometimes +als hardwire the output divider. They therefore have special compatible +strings as per this table (the OD value is the value on the pins, not the +resulting output divider): + +Integrator variant: RDW OD VDW + +Integrator/AP 22 1 Bit 8 0, rest variable +integratorap-cm + +Integrator/AP 46 3 Bit 8 0, rest variable +integratorap-sys + +Integrator/AP 22 or 1 17 or (33 or 25 MHz) +integratorap-pci 14 1 14 + +Integrator/CP 22 variable Bit 8 0, rest variable +integratorcp-cm-core + +Integrator/CP 22 variable Bit 8 0, rest variable +integratorcp-cm-mem + The ICST oscillator must be provided inside a system controller node. Required properties: +- compatible: must be one of + "arm,syscon-icst525" + "arm,syscon-icst307" + "arm,syscon-icst525-integratorap-cm" + "arm,syscon-icst525-integratorap-sys" + "arm,syscon-icst525-integratorap-pci" + "arm,syscon-icst525-integratorcp-cm-core" + "arm,syscon-icst525-integratorcp-cm-mem" - lock-offset: the offset address into the system controller where the unlocking register is located - vco-offset: the offset address into the system controller where the ICST control register is located (even 32 bit address) -- compatible: must be one of "arm,syscon-icst525" or "arm,syscon-icst307" - #clock-cells: must be <0> - clocks: parent clock, since the ICST needs a parent clock to derive its frequency from, this attribute is compulsory.