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[209.132.180.67]) by mx.google.com with ESMTP id er10si25034111pac.38.2016.08.22.02.19.52; Mon, 22 Aug 2016 02:19:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752984AbcHVJTw (ORCPT + 7 others); Mon, 22 Aug 2016 05:19:52 -0400 Received: from mail-lf0-f44.google.com ([209.85.215.44]:36175 "EHLO mail-lf0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751754AbcHVJTv (ORCPT ); Mon, 22 Aug 2016 05:19:51 -0400 Received: by mail-lf0-f44.google.com with SMTP id g62so73008537lfe.3 for ; Mon, 22 Aug 2016 02:19:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=Tg+zuGU6FufzdvTA0nY7Cicntts/MgEdTJvkioevw78=; b=WIU/eiSWZs0eLw4sAyQh0lW34VX+qZeOtuWkM71pIsucGA+I2+nL3pU0Co+gQ5iyUa tIXLw3idVvWqU/+GosUM3aoeM7xUoNJQIQ7Ycbt1Gi45SwViaMXjBrl5BpyIK21Cx8oT ECejGV+rmTHPMYLjK/zngum76w52E+O8P9GDM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Tg+zuGU6FufzdvTA0nY7Cicntts/MgEdTJvkioevw78=; b=CKa7KxPoTmCI6Cytn3wLGZA4PqEkEicp0xz4MNqAETworcwj8sHCzllJag+hg9Vfj/ Xm2OD8RQVFXJz720KBCpdPkDAFukTXLsTIkRS84DdqGwFgKWwpDmwGCCFFspaOKFTObK hKCPQJ9wDK7YVI+ZnvyX2D1DItjLv7yHRQGYvmFa3Gelbr/aYWw/nFOPfxlMYOmoozNQ b2AF7VU47P2a7eR2ZOFSwHs5CY6h+OBrJuy6iTZ79FYDls3tWO/LxSwYF/faeT6ovh7h TLM5eR2QqtG4elJoBpGDropfSlUm0mi/jyWvy+EaEAHp9sNNuqv+XLxuxd7MKum3ac+k rYHg== X-Gm-Message-State: AEkoous9jemnqdd5KS4qPRe9zQY9TFoc3tpEI+48RRAgxFqVDomS7VrUzmawbI7MtezE/jBb X-Received: by 10.25.17.228 with SMTP id 97mr5626666lfr.154.1471857589593; Mon, 22 Aug 2016 02:19:49 -0700 (PDT) Received: from linuslaptop.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id 93sm3596854ljb.20.2016.08.22.02.19.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Aug 2016 02:19:48 -0700 (PDT) From: Linus Walleij To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, Linus Walleij , devicetree@vger.kernel.org, Russell King Subject: [PATCH 1/3 v2] clk: versatile add DT bindings for the ICST CM variants Date: Mon, 22 Aug 2016 11:19:32 +0200 Message-Id: <1471857574-13125-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Integrator/AP and Integrator/CP core modules have special versions of the ICST525 interface hardcoding some bits. Create special compatible strings to identify these variants, also explain a bit what is going on. Cc: devicetree@vger.kernel.org Cc: Russell King Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Fix spelling mistakes. - Try to be less specific and more general about the ARM system controllers so we do not need to edit the text again for the next variant we discover. --- .../devicetree/bindings/clock/arm-syscon-icst.txt | 34 ++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt index 8b7177cecb36..27468119fd94 100644 --- a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt +++ b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt @@ -5,20 +5,50 @@ Technology (IDT). ARM integrated these oscillators deeply into their reference designs by adding special control registers that manage such oscillators to their system controllers. -The ARM system controller contains logic to serialize and initialize +The various ARM system controllers contain logic to serialize and initialize an ICST clock request after a write to the 32 bit register at an offset into the system controller. Furthermore, to even be able to alter one of these frequencies, the system controller must first be unlocked by writing a special token to another offset in the system controller. +Some ARM hardware contain special versions of the serial interface that only +connects the low 8 bits of the VDW (missing one bit), hardwires RDW to +different values and sometimes also hardwire the output divider. They +therefore have special compatible strings as per this table (the OD value is +the value on the pins, not the resulting output divider): + +Hardware variant: RDW OD VDW + +Integrator/AP 22 1 Bit 8 0, rest variable +integratorap-cm + +Integrator/AP 46 3 Bit 8 0, rest variable +integratorap-sys + +Integrator/AP 22 or 1 17 or (33 or 25 MHz) +integratorap-pci 14 1 14 + +Integrator/CP 22 variable Bit 8 0, rest variable +integratorcp-cm-core + +Integrator/CP 22 variable Bit 8 0, rest variable +integratorcp-cm-mem + The ICST oscillator must be provided inside a system controller node. Required properties: +- compatible: must be one of + "arm,syscon-icst525" + "arm,syscon-icst307" + "arm,syscon-icst525-integratorap-cm" + "arm,syscon-icst525-integratorap-sys" + "arm,syscon-icst525-integratorap-pci" + "arm,syscon-icst525-integratorcp-cm-core" + "arm,syscon-icst525-integratorcp-cm-mem" - lock-offset: the offset address into the system controller where the unlocking register is located - vco-offset: the offset address into the system controller where the ICST control register is located (even 32 bit address) -- compatible: must be one of "arm,syscon-icst525" or "arm,syscon-icst307" - #clock-cells: must be <0> - clocks: parent clock, since the ICST needs a parent clock to derive its frequency from, this attribute is compulsory.