From patchwork Mon Sep 12 09:15:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 75975 Delivered-To: patch@linaro.org Received: by 10.140.106.72 with SMTP id d66csp751760qgf; Mon, 12 Sep 2016 02:16:21 -0700 (PDT) X-Received: by 10.98.159.26 with SMTP id g26mr13898473pfe.137.1473671780815; Mon, 12 Sep 2016 02:16:20 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w8si20826193paj.25.2016.09.12.02.16.20; Mon, 12 Sep 2016 02:16:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757415AbcILJQL (ORCPT + 7 others); Mon, 12 Sep 2016 05:16:11 -0400 Received: from mail-wm0-f41.google.com ([74.125.82.41]:37768 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757360AbcILJQK (ORCPT ); Mon, 12 Sep 2016 05:16:10 -0400 Received: by mail-wm0-f41.google.com with SMTP id c131so46570622wmh.0 for ; Mon, 12 Sep 2016 02:16:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dKWgDuI2zCACJcLqwB+aG9BJVKBjXKGUnCMo12Nsxdo=; b=NZwFwE4hrJaAbUsavJJfeYco052sAKswzWIXCpBZvpDWHQpffeiSDmx6rCjnsiK2Xq zp/LLNv+fxIWnytm9S5fa/WMKnn/Bjr8vIGg8fKjhTF8gLgEN7wUvYVPE7DSucrqMK6d xW27MSVxKb+jiVyWd3kDn7pbU+qEAIzopUlvo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dKWgDuI2zCACJcLqwB+aG9BJVKBjXKGUnCMo12Nsxdo=; b=Z18tC9VO4OD3bAtlqPd2abzpOFSupxWF0DnMiab1VmOFz4U+iC6SjIBzuyc1eZZSoB QaWAN/7TiGiuyAGqhcywFPlQFdkMCUAde+fy/1943165nJxekz+4SejFg2/v73sPDsUH 4SyOjFFVdtO8J2/fX3tIOKWtBA7Z/Ub+VNE+gYvRwjpGbEXN7k3/aABsRxFoHri9zhMA 2TO6lNRavoBhyy9YvqzSLEFhQmNqBbBFSW9eG9wxAH72tBhSMqOp7k9b3fo2rniLbyBn Py0BJgXlHKVVbTYhcZIJznTFKWel5nshND6RJ4UGCeQtUeF0JKaefEgTgsZdyYNNihTF MANg== X-Gm-Message-State: AE9vXwMvaEpbIyz4u155UdANYac+HnWmks1n1AH/qRn++MOwzUH1KJRvxPfAiQzDsBNizh/o X-Received: by 10.28.157.139 with SMTP id g133mr9220805wme.82.1473671767968; Mon, 12 Sep 2016 02:16:07 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:e089:f01a:f419:f17e]) by smtp.gmail.com with ESMTPSA id va3sm16939362wjb.18.2016.09.12.02.16.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 12 Sep 2016 02:16:07 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: mingo@kernel.org, linux-kernel@vger.kernel.org, Joel Stanley , Rob Herring , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 3/9] clocksource/drivers/moxart: Add Aspeed support Date: Mon, 12 Sep 2016 11:15:41 +0200 Message-Id: <1473671747-9400-3-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473671747-9400-1-git-send-email-daniel.lezcano@linaro.org> References: <1473671747-9400-1-git-send-email-daniel.lezcano@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Joel Stanley The Aspeed SoC has timer IP with a very similar register layout to the moxart timer. This patch adds support for the fourth and fifth gen aspeed SoCs, and has been tested on the ast2400 and ast2500. Signed-off-by: Joel Stanley Acked-by: Rob Herring Signed-off-by: Daniel Lezcano --- .../bindings/timer/moxa,moxart-timer.txt | 4 ++- drivers/clocksource/moxart_timer.c | 32 ++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt index da2d510..e207c11 100644 --- a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt +++ b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt @@ -2,7 +2,9 @@ MOXA ART timer Required properties: -- compatible : Must be "moxa,moxart-timer" +- compatible : Must be one of: + - "moxa,moxart-timer" + - "aspeed,ast2400-timer" - reg : Should contain registers location and length - interrupts : Should contain the timer interrupt number - clocks : Should contain phandle for the clock that drives the counter diff --git a/drivers/clocksource/moxart_timer.c b/drivers/clocksource/moxart_timer.c index cb0b347..ad2bead9 100644 --- a/drivers/clocksource/moxart_timer.c +++ b/drivers/clocksource/moxart_timer.c @@ -56,6 +56,23 @@ #define MOXART_TIMER1_ENABLE (MOXART_CR_2_ENABLE | MOXART_CR_1_ENABLE) #define MOXART_TIMER1_DISABLE (MOXART_CR_2_ENABLE) +/* + * The ASpeed variant of the IP block has a different layout + * for the control register + */ +#define ASPEED_CR_1_ENABLE BIT(0) +#define ASPEED_CR_1_CLOCK BIT(1) +#define ASPEED_CR_1_INT BIT(2) +#define ASPEED_CR_2_ENABLE BIT(4) +#define ASPEED_CR_2_CLOCK BIT(5) +#define ASPEED_CR_2_INT BIT(6) +#define ASPEED_CR_3_ENABLE BIT(8) +#define ASPEED_CR_3_CLOCK BIT(9) +#define ASPEED_CR_3_INT BIT(10) + +#define ASPEED_TIMER1_ENABLE (ASPEED_CR_2_ENABLE | ASPEED_CR_1_ENABLE) +#define ASPEED_TIMER1_DISABLE (ASPEED_CR_2_ENABLE) + struct moxart_timer { void __iomem *base; unsigned int t1_disable_val; @@ -165,6 +182,9 @@ static int __init moxart_timer_init(struct device_node *node) if (of_device_is_compatible(node, "moxa,moxart-timer")) { timer->t1_enable_val = MOXART_TIMER1_ENABLE; timer->t1_disable_val = MOXART_TIMER1_DISABLE; + } else if (of_device_is_compatible(node, "aspeed,ast2400-timer")) { + timer->t1_enable_val = ASPEED_TIMER1_ENABLE; + timer->t1_disable_val = ASPEED_TIMER1_DISABLE; } else panic("%s: unknown platform\n", node->full_name); @@ -200,6 +220,17 @@ static int __init moxart_timer_init(struct device_node *node) return ret; } + /* Clear match registers */ + writel(0, timer->base + TIMER1_BASE + REG_MATCH1); + writel(0, timer->base + TIMER1_BASE + REG_MATCH2); + writel(0, timer->base + TIMER2_BASE + REG_MATCH1); + writel(0, timer->base + TIMER2_BASE + REG_MATCH2); + + /* + * Start timer 2 rolling as our main wall clock source, keep timer 1 + * disabled + */ + writel(0, timer->base + TIMER_CR); writel(~0, timer->base + TIMER2_BASE + REG_LOAD); writel(timer->t1_disable_val, timer->base + TIMER_CR); @@ -214,3 +245,4 @@ static int __init moxart_timer_init(struct device_node *node) return 0; } CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init); +CLOCKSOURCE_OF_DECLARE(aspeed, "aspeed,ast2400-timer", moxart_timer_init);