From patchwork Thu Oct 27 07:34:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 79625 Delivered-To: patch@linaro.org Received: by 10.80.142.83 with SMTP id 19csp494352edx; Thu, 27 Oct 2016 00:35:58 -0700 (PDT) X-Received: by 10.98.217.135 with SMTP id b7mr11951302pfl.103.1477553757921; Thu, 27 Oct 2016 00:35:57 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t18si6514411pge.118.2016.10.27.00.35.57; Thu, 27 Oct 2016 00:35:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933890AbcJ0Hf5 (ORCPT + 7 others); Thu, 27 Oct 2016 03:35:57 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:35744 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933572AbcJ0Hf4 (ORCPT ); Thu, 27 Oct 2016 03:35:56 -0400 Received: from 172.24.1.60 (EHLO szxeml431-hub.china.huawei.com) ([172.24.1.60]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DPS29459; Thu, 27 Oct 2016 15:34:27 +0800 (CST) Received: from localhost (10.177.23.32) by szxeml431-hub.china.huawei.com (10.82.67.208) with Microsoft SMTP Server id 14.3.235.1; Thu, 27 Oct 2016 15:34:17 +0800 From: Ding Tianhong To: , , , , , , , , , CC: Ding Tianhong Subject: [PATCH v2 2/4] arm64: arch_timer: Introduce a generic erratum handing mechanism for fsl-a008585 Date: Thu, 27 Oct 2016 15:34:09 +0800 Message-ID: <1477553651-13428-2-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1477553651-13428-1-git-send-email-dingtianhong@huawei.com> References: <1477553651-13428-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The workaround for hisilicon,161601 will check the return value of the system counter by different way, in order to distinguish with the fsl-a008585 workaround, introduce a new generic erratum handing mechanism for fsl-a008585 and rename some functions. v2: Introducing a new generic erratum handling mechanism for fsl erratum a008585. Signed-off-by: Ding Tianhong --- arch/arm64/include/asm/arch_timer.h | 20 +++++++++----- drivers/clocksource/arm_arch_timer.c | 51 +++++++++++++++++++++--------------- 2 files changed, 43 insertions(+), 28 deletions(-) -- 1.9.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index eaa5bbe..118719d8 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -31,15 +31,21 @@ #if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) extern struct static_key_false arch_timer_read_ool_enabled; -#define needs_fsl_a008585_workaround() \ +#define needs_timer_erratum_workaround() \ static_branch_unlikely(&arch_timer_read_ool_enabled) #else -#define needs_fsl_a008585_workaround() false +#define needs_timer_erratum_workaround() false #endif -u32 __fsl_a008585_read_cntp_tval_el0(void); -u32 __fsl_a008585_read_cntv_tval_el0(void); -u64 __fsl_a008585_read_cntvct_el0(void); + +struct arch_timer_erratum_workaround { + int erratum; + u32 (*read_cntp_tval_el0)(void); + u32 (*read_cntv_tval_el0)(void); + u64 (*read_cntvct_el0)(void); +}; + +extern struct arch_timer_erratum_workaround *erratum_workaround; /* * The number of retries is an arbitrary value well beyond the highest number @@ -62,8 +68,8 @@ u64 __fsl_a008585_read_cntvct_el0(void); #define arch_timer_reg_read_stable(reg) \ ({ \ u64 _val; \ - if (needs_fsl_a008585_workaround()) \ - _val = __fsl_a008585_read_##reg(); \ + if (needs_timer_erratum_workaround()) \ + _val = erratum_workaround->read_##reg(); \ else \ _val = read_sysreg(reg); \ _val; \ diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 73c487d..e4f7fa1 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -95,10 +95,32 @@ early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg); */ #ifdef CONFIG_FSL_ERRATUM_A008585 +struct arch_timer_erratum_workaround *erratum_workaround = NULL; + DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled); EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled); -static int fsl_a008585_enable = -1; + +static u32 fsl_a008585_read_cntp_tval_el0(void) +{ + return __fsl_a008585_read_reg(cntp_tval_el0); +} + +static u32 fsl_a008585_read_cntv_tval_el0(void) +{ + return __fsl_a008585_read_reg(cntv_tval_el0); +} + +static u64 fsl_a008585_read_cntvct_el0(void) +{ + return __fsl_a008585_read_reg(cntvct_el0); +} + +static struct arch_timer_erratum_workaround arch_timer_fsl_a008585 = { + .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0, + .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0, + .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, +}; static int __init early_fsl_a008585_cfg(char *buf) { @@ -109,26 +131,12 @@ static int __init early_fsl_a008585_cfg(char *buf) if (ret) return ret; - fsl_a008585_enable = val; + if (val) + erratum_workaround = &arch_timer_fsl_a008585; + return 0; } early_param("clocksource.arm_arch_timer.fsl-a008585", early_fsl_a008585_cfg); - -u32 __fsl_a008585_read_cntp_tval_el0(void) -{ - return __fsl_a008585_read_reg(cntp_tval_el0); -} - -u32 __fsl_a008585_read_cntv_tval_el0(void) -{ - return __fsl_a008585_read_reg(cntv_tval_el0); -} - -u64 __fsl_a008585_read_cntvct_el0(void) -{ - return __fsl_a008585_read_reg(cntvct_el0); -} -EXPORT_SYMBOL(__fsl_a008585_read_cntvct_el0); #endif /* CONFIG_FSL_ERRATUM_A008585 */ static __always_inline @@ -891,9 +899,10 @@ static int __init arch_timer_of_init(struct device_node *np) arch_timer_c3stop = !of_property_read_bool(np, "always-on"); #ifdef CONFIG_FSL_ERRATUM_A008585 - if (fsl_a008585_enable < 0) - fsl_a008585_enable = of_property_read_bool(np, "fsl,erratum-a008585"); - if (fsl_a008585_enable) { + if (!erratum_workaround && of_property_read_bool(np, "fsl,erratum-a008585")) + erratum_workaround = &arch_timer_fsl_a008585; + + if (erratum_workaround) { static_branch_enable(&arch_timer_read_ool_enabled); pr_info("Enabling workaround for FSL erratum A-008585\n"); }