From patchwork Tue Nov 22 09:44:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 83361 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp2004904qge; Tue, 22 Nov 2016 01:44:54 -0800 (PST) X-Received: by 10.99.232.21 with SMTP id s21mr42546223pgh.19.1479807894919; Tue, 22 Nov 2016 01:44:54 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k189si27589452pgd.312.2016.11.22.01.44.54; Tue, 22 Nov 2016 01:44:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755444AbcKVJox (ORCPT + 7 others); Tue, 22 Nov 2016 04:44:53 -0500 Received: from mail-wm0-f48.google.com ([74.125.82.48]:37485 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753324AbcKVJov (ORCPT ); Tue, 22 Nov 2016 04:44:51 -0500 Received: by mail-wm0-f48.google.com with SMTP id t79so15218482wmt.0 for ; Tue, 22 Nov 2016 01:44:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7xtzavZIXXmcSBY5/yJ1hBbT/T9kahoauHb7Tcj1/pQ=; b=LiWCMJQhxH1fEv3q+XH6LheGND9rQQmLJlZhuPnTqfXh6miy3bFGdOhcMKFzRQb4HF VeTVoEN92Egrse1O72fgTNJ7Rshc+jZMXo5+yg1s2/BpQZZWVV7cI5yVCO58Tci6vxPN hVCERasOp4p7243Up5DpMKqDhPxXXzh91MDiw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7xtzavZIXXmcSBY5/yJ1hBbT/T9kahoauHb7Tcj1/pQ=; b=IyuvWnLYZ4P4aP/KLMkZl50hsTgfj/86K4//sJCGBh8yWYksqm36HR6/x2m1bcW5gk 6Tc6LYT+IpAAOL/4x1/6wBLC7HyZeAAE5ftYa04VQAq8gVOAEMugqGj7ETgzhXLyTCeo oeN215S8TuuaK/5CimSjs4w26xjVSwSaSSltWKqT70AdJARNtMvOpzyzpSrciP73v/tr ftEVZNNVJ3lc/VXIaDO6ebkZfRfFxszcjE1wIjhySu7k17Kkq6VRGqfWbDaSLqt8B62X dLlKuZHrkXPDn1B0idtYKhsxHlGz6SAwBVg1wyR3P4X+WD5jgRg9XJ/qiSQZZItWdMSL LT2A== X-Gm-Message-State: AKaTC03+yoacM6Accu9+pfBqPs8IUkCFf6x0PDtt/c2T0sgz8Yz3IWGAlD+qhi53SjwfInTs X-Received: by 10.194.205.73 with SMTP id le9mr13210304wjc.31.1479807889553; Tue, 22 Nov 2016 01:44:49 -0800 (PST) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:d4cd:7489:29a3:d5ed]) by smtp.gmail.com with ESMTPSA id ab10sm29789450wjc.45.2016.11.22.01.44.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 Nov 2016 01:44:49 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Brian Norris , Marc Zyngier , Rob Herring , Mark Rutland , Will Deacon , Douglas Anderson , Scott Wood , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM ARCHITECTED TIMER DRIVER) Subject: [PATCH 1/4] clocksource/drivers/arm_arch_timer: Don't assume clock runs in suspend Date: Tue, 22 Nov 2016 10:44:21 +0100 Message-Id: <1479807866-6957-1-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <20161122094300.GA2017@mai> References: <20161122094300.GA2017@mai> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Brian Norris The ARM specifies that the system counter "must be implemented in an always-on power domain," and so we try to use the counter as a source of timekeeping across suspend/resume. Unfortunately, some SoCs (e.g., Rockchip's RK3399) do not keep the counter ticking properly when switched from their high-power clock to the lower-power clock used in system suspend. Support this quirk by adding a new device tree property. Signed-off-by: Brian Norris Reviewed-by: Douglas Anderson Acked-by: Marc Zyngier Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/arm/arch_timer.txt | 5 +++++ drivers/clocksource/arm_arch_timer.c | 9 ++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index ef5fbe9..ad440a2 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -38,6 +38,11 @@ to deliver its interrupts via SPIs. architecturally-defined reset values. Only supported for 32-bit systems which follow the ARMv7 architected reset values. +- arm,no-tick-in-suspend : The main counter does not tick when the system is in + low-power system suspend on some SoCs. This behavior does not match the + Architecture Reference Manual's specification that the system counter "must + be implemented in an always-on power domain." + Example: diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 73c487d..a2503db 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -81,6 +81,7 @@ static struct clock_event_device __percpu *arch_timer_evt; static enum ppi_nr arch_timer_uses_ppi = VIRT_PPI; static bool arch_timer_c3stop; static bool arch_timer_mem_use_virtual; +static bool arch_counter_suspend_stop; static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM); @@ -576,7 +577,7 @@ static struct clocksource clocksource_counter = { .rating = 400, .read = arch_counter_read, .mask = CLOCKSOURCE_MASK(56), - .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; static struct cyclecounter cyclecounter = { @@ -616,6 +617,8 @@ static void __init arch_counter_register(unsigned type) arch_timer_read_counter = arch_counter_get_cntvct_mem; } + if (!arch_counter_suspend_stop) + clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; start_count = arch_timer_read_counter(); clocksource_register_hz(&clocksource_counter, arch_timer_rate); cyclecounter.mult = clocksource_counter.mult; @@ -907,6 +910,10 @@ static int __init arch_timer_of_init(struct device_node *np) of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) arch_timer_uses_ppi = PHYS_SECURE_PPI; + /* On some systems, the counter stops ticking when in suspend. */ + arch_counter_suspend_stop = of_property_read_bool(np, + "arm,no-tick-in-suspend"); + return arch_timer_init(); } CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);