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[209.132.180.67]) by mx.google.com with ESMTP id l78si66536304pfg.206.2016.11.30.16.49.20; Wed, 30 Nov 2016 16:49:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757562AbcLAAtP (ORCPT + 7 others); Wed, 30 Nov 2016 19:49:15 -0500 Received: from mail-pf0-f169.google.com ([209.85.192.169]:36522 "EHLO mail-pf0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755042AbcLAAtO (ORCPT ); Wed, 30 Nov 2016 19:49:14 -0500 Received: by mail-pf0-f169.google.com with SMTP id 189so42140779pfz.3 for ; Wed, 30 Nov 2016 16:49:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iMSbsmSlRvxDEwWdJ0jved8vF7k9QSaxW3IPHWmu8oA=; b=KC7R87odLfc3TH6lqe5ZIcofBYbxKpGM/4nt1Y3QgMkDFGx4MhlK1EfGSdgtGRTJ1s r0i4GDj3v9UFUM/terMSfEdBXFTXWMKagtGh/SeASLLyAQyThFSVEKFWqJWJiab6K7eb rGjNivnpd1wAKcIcSObfd7iL9mkjYKp75o+Lk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iMSbsmSlRvxDEwWdJ0jved8vF7k9QSaxW3IPHWmu8oA=; b=amx1W7nsE3/+QWoUIxyijX5GHqQxzif9/UB7aj4EfJA1bYYP5Cbg1Ll995t6hDRfsy Mw1GNPeDIc+Dq/GgcLPUQxmVk1R/UsNDNmIabRdP3DK4o/Wj/w4CTtxkOc7+rYet2vou IUoWl17W6zUGoftdsoP/HCJjFNPzKtFZrcJw1cY1u5gOcveky8gowG6JJb93AVkJxh83 ru/14jvrXeYxHr9Bf+HSLce5ubYk3rqUULFRpifFhrPzX7hZY5t3x+oAKuQw2MkNFuZ4 UofWWSu3bVAMEils+cqmOpFpsEGNDZRzrrsSymL4fC4nfVicBJZste/ss3fZ7QP+ipRG 84Kw== X-Gm-Message-State: AKaTC006xsZXctxM0dBhQj0IlxRc76XRUKnfeS5Z697ok9DdTfyEeMqXPFtc1FkheDS4P4Hz X-Received: by 10.99.218.85 with SMTP id l21mr64606800pgj.102.1480553354081; Wed, 30 Nov 2016 16:49:14 -0800 (PST) Received: from localhost.localdomain ([104.237.91.22]) by smtp.gmail.com with ESMTPSA id w11sm93408530pfk.75.2016.11.30.16.49.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 Nov 2016 16:49:13 -0800 (PST) From: Zhangfei Gao To: Rob Herring , Philipp Zabel , Arnd Bergmann Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Zhangfei Gao Subject: [resend v2: PATCH 1/2] dt-bindings: Document the hi3660 reset bindings Date: Thu, 1 Dec 2016 08:48:40 +0800 Message-Id: <1480553321-17400-2-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1480553321-17400-1-git-send-email-zhangfei.gao@linaro.org> References: <1480553321-17400-1-git-send-email-zhangfei.gao@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings documentation for hi3660 SoC reset controller. Signed-off-by: Zhangfei Gao --- .../bindings/reset/hisilicon,hi3660-reset.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt new file mode 100644 index 0000000..250daf2 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt @@ -0,0 +1,51 @@ +Hisilicon System Reset Controller +====================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +The reset controller registers are part of the system-ctl block on +hi3660 SoC. + +Required properties: +- compatible: should be + "hisilicon,hi3660-reset" +- #reset-cells: 1, see below +- hisi,rst-syscon: phandle of the reset's syscon. +- hisi,reset-bits: Contains the reset control register information + Should contain 2 cells for each reset exposed to + consumers, defined as: + Cell #1 : offset from the syscon register base + Cell #2 : bits position of the control register + +Example: + iomcu: iomcu@ffd7e000 { + compatible = "hisilicon,hi3660-iomcu", "syscon"; + reg = <0x0 0xffd7e000 0x0 0x1000>; + }; + + iomcu_rst: iomcu_rst_controller { + compatible = "hisilicon,hi3660-reset"; + #reset-cells = <1>; + hisi,rst-syscon = <&iomcu>; + hisi,reset-bits = <0x20 0x8 /* 0: i2c0 */ + 0x20 0x10 /* 1: i2c1 */ + 0x20 0x20 /* 2: i2c2 */ + 0x20 0x8000000>; /* 3: i2c6 */ + }; + +Specifying reset lines connected to IP modules +============================================== +example: + + i2c0: i2c@..... { + ... + resets = <&iomcu_rst 0>; + ... + }; + + i2c1: i2c@..... { + ... + resets = <&iomcu_rst 1>; + ... + };