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[172.104.47.128]) by smtp.gmail.com with ESMTPSA id m25sm5801020pfk.15.2017.05.17.18.51.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 May 2017 18:51:26 -0700 (PDT) From: Leo Yan To: Wei Xu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Guodong Xu , Zhong Kaihua , Chen Jun , Zhangfei Gao , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Daniel Lezcano Cc: Leo Yan Subject: [PATCH v2 2/2] arm64: dts: add sp804 timer node for Hi3660 Date: Thu, 18 May 2017 09:50:47 +0800 Message-Id: <1495072247-25217-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495072247-25217-1-git-send-email-leo.yan@linaro.org> References: <1495072247-25217-1-git-send-email-leo.yan@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Hi3660 SoC comes with the sp804 timer in addition to the architecture timers. These ones are shutdown when reaching a deep idle states and a backup timer is needed. The sp804 belongs to another power domain and can fulfill the purpose of replacing temporarily an architecture timer when the CPU is idle. Describe it in the device tree, so it can be enabled at boot time. Suggested-by: Daniel Lezcano Acked-by: Daniel Lezcano Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 138fcba..f75c792 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -173,6 +173,17 @@ #clock-cells = <1>; }; + dual_timer0: timer@fff14000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfff14000 0x0 0x1000>; + interrupts = , + ; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + ufs: ufs@ff3b0000 { compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs"; reg = <0x0 0xff3b0000 0x0 0x1000>, /* 0: HCI standard */