From patchwork Thu Dec 20 05:23:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 154310 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp5751801ljp; Wed, 19 Dec 2018 21:23:34 -0800 (PST) X-Google-Smtp-Source: AFSGD/WyF8jfAdufdhsXY4eQUh+4kuVGzFNBOvPkjw8rX0ToxMFaNLp9DcOCrTuepjJIqLwqEeNa X-Received: by 2002:a17:902:bc3:: with SMTP id 61mr22994137plr.15.1545283414436; Wed, 19 Dec 2018 21:23:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545283414; cv=none; d=google.com; s=arc-20160816; b=Bq1CBO9QaSRcOFmqSDgTlqSx0PrTblRY0JiTPF8m5uAf1tXDOlUvzJtqybKJvV6QnC U6oNNaDXUkDNo18X5F0heLww8HA+wHZGURv20C93qR4+Wke9LVI8y4YP9qr3VXnP87hj z0GqXEYVI8LkWp+1Z1kA4FJmnybuZw2o7a4CXAsUjfQY4qKIx921Eye0OUC9NCBawXtp Okyqtobz+7V1reVY+BqrPzSedaPA6Pj+xIsBt70082KfNbmqn1JMp/wtfAyzHumd0Rov j/wqYqmgFBx62lpWBbQOMnWgPoFLkDdi+ECeemYp8Ptsm1sGyvwJIe4cP8ycqgOcT8AD j7mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=zIyeBdV5OUUmsTF+hmoiQg6SW/XVQg+FDHnN8qT4ipQ=; b=I89gU4LQxje6ucAXiwl41BluDL60wZ5IdqettMl82Cv47AEosaYxjuFslt+mlF1/yg rLW/2jQXrslb1OpYJzsO8IYdabiYME269rsqQmWWn1An2mWwPoxahStyRfKf4VWB/iUb 41bBnHxu8V1y+QCFghORQbsYwGzb10zTE2YbnKD0m0O0df+iW7fltUm8NqTCsNmdKvpS fUbTHTwD+0RdYdMKuI+D666fUb0/zpbOeRSXzd8dQxK7xCpIdKM8svii59/wasQJe3xu zn1Bu2+Ch8W1cGdh5vss0XPYpV06TwCelvjb6AsoCj1u5rdA5D4eDbMgEvnXJUhduko6 40+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id go3si16801387plb.97.2018.12.19.21.23.34; Wed, 19 Dec 2018 21:23:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729566AbeLTFXc (ORCPT + 6 others); Thu, 20 Dec 2018 00:23:32 -0500 Received: from mx.socionext.com ([202.248.49.38]:30094 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725550AbeLTFXc (ORCPT ); Thu, 20 Dec 2018 00:23:32 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 20 Dec 2018 14:23:30 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 02CAB180D80; Thu, 20 Dec 2018 14:23:31 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 20 Dec 2018 14:23:30 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 9E6F31A1235; Thu, 20 Dec 2018 14:23:30 +0900 (JST) From: Kunihiko Hayashi To: Masahiro Yamada Cc: Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH] arm64: dts: uniphier: Add PCIe host controller and PHY nodes Date: Thu, 20 Dec 2018 14:23:13 +0900 Message-Id: <1545283393-2078-1-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add PCIe host controller and PHY nodes. This supports for LD20, PXs3 and their boards. This node defines PCIe memory, I/O, and config spaces as follows. MEM: 20000000-2ffdffff (255MB) I/O: 2ffe0000-2ffeffff ( 64KB) CFG: 2fff0000-2fffffff ( 64KB) Signed-off-by: Kunihiko Hayashi --- arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 47 ++++++++++++++++++++++ .../arm64/boot/dts/socionext/uniphier-pxs3-ref.dts | 4 ++ arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 47 ++++++++++++++++++++++ 3 files changed, 98 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index d7e2d89..63d3d17 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -872,6 +872,53 @@ }; }; + pcie: pcie@66000000 { + compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; + status = "disabled"; + reg-names = "dbi", "link", "config"; + reg = <0x66000000 0x1000>, <0x66010000 0x10000>, + <0x2fff0000 0x10000>; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + num-lanes = <1>; + num-viewport = <1>; + bus-range = <0x0 0xff>; + device_type = "pci"; + ranges = + /* downstream I/O */ + <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000 + /* non-prefetchable memory */ + 0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; + #interrupt-cells = <1>; + interrupt-names = "dma", "msi"; + interrupts = <0 224 4>, <0 225 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ + <0 0 0 2 &pcie_intc 1>, /* INTB */ + <0 0 0 3 &pcie_intc 2>, /* INTC */ + <0 0 0 4 &pcie_intc 3>; /* INTD */ + phy-names = "pcie-phy"; + phys = <&pcie_phy>; + + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <0 226 4>; + }; + }; + + pcie_phy: phy@66038000 { + compatible = "socionext,uniphier-ld20-pcie-phy"; + reg = <0x66038000 0x4000>; + #phy-cells = <0>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + socionext,syscon = <&soc_glue>; + }; + nand: nand@68000000 { compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts index a41f7ca..f91d77f 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts @@ -112,3 +112,7 @@ &usb1 { status = "okay"; }; + +&pcie { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 4f57c9e..fe56a32 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -727,6 +727,53 @@ }; }; + pcie: pcie@66000000 { + compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; + status = "disabled"; + reg-names = "dbi", "link", "config"; + reg = <0x66000000 0x1000>, <0x66010000 0x10000>, + <0x2fff0000 0x10000>; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + num-lanes = <1>; + num-viewport = <1>; + bus-range = <0x0 0xff>; + device_type = "pci"; + ranges = + /* downstream I/O */ + <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000 + /* non-prefetchable memory */ + 0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; + #interrupt-cells = <1>; + interrupt-names = "dma", "msi"; + interrupts = <0 224 4>, <0 225 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ + <0 0 0 2 &pcie_intc 1>, /* INTB */ + <0 0 0 3 &pcie_intc 2>, /* INTC */ + <0 0 0 4 &pcie_intc 3>; /* INTD */ + phy-names = "pcie-phy"; + phys = <&pcie_phy>; + + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <0 226 4>; + }; + }; + + pcie_phy: phy@66038000 { + compatible = "socionext,uniphier-pxs3-pcie-phy"; + reg = <0x66038000 0x4000>; + #phy-cells = <0>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + socionext,syscon = <&soc_glue>; + }; + nand: nand@68000000 { compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled";