From patchwork Fri Jan 3 03:12:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 206234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFEACC32770 for ; Fri, 3 Jan 2020 03:13:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 88261222C3 for ; Fri, 3 Jan 2020 03:13:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="l8OwAzzZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727634AbgACDNh (ORCPT ); Thu, 2 Jan 2020 22:13:37 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:51303 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727404AbgACDMr (ORCPT ); Thu, 2 Jan 2020 22:12:47 -0500 X-UUID: 7b3c5b98949e4d2084d774c8b415f5b0-20200103 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zLLZC00K/D+nIAyTwOOL8PcRQJSTuzpvNAs2qK6gIqU=; b=l8OwAzzZO/MOr9qfK9bEzzmoDZCywzj4mEJErj8o7Liu+Xf7rMRcLzmFcOyzWp0ypY0LWJ7bDs5hXjGVWOS9tZz4Dw/Skwh2K5RC+JcForXu3EA/k8PM/yhEjPuWPhRmn0Lv9q5jQYl80fmEFozLOZ7glhV7wtCu6i9+/pLkWg4=; X-UUID: 7b3c5b98949e4d2084d774c8b415f5b0-20200103 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 58300790; Fri, 03 Jan 2020 11:12:40 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 3 Jan 2020 11:12:08 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 3 Jan 2020 11:13:06 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger CC: David Airlie , Daniel Vetter , Mark Rutland , , , , , , Yongqiang Niu Subject: [RESEND PATCH v6 03/17] drm/mediatek: move dsi/dpi select input into mtk_ddp_sel_in Date: Fri, 3 Jan 2020 11:12:14 +0800 Message-ID: <1578021148-32413-4-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1578021148-32413-1-git-send-email-yongqiang.niu@mediatek.com> References: <1578021148-32413-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org move dsi/dpi select input into mtk_ddp_sel_in DPI_SEL_IN_BLS is zero, it is same with hardware default setting, DISP_REG_CONFIG_DPI_SEL no need set when bls connect with dpi0 Signed-off-by: Yongqiang Niu --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) -- 1.8.1.1.dirty diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 39700b9..d66ce31 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -376,6 +376,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { *addr = DISP_REG_CONFIG_DSI_SEL; value = DSI_SEL_IN_BLS; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_RDMA; } else { value = 0; } @@ -393,10 +396,6 @@ static void mtk_ddp_sout_sel(struct regmap *config_regs, } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { regmap_write(config_regs, DISP_REG_CONFIG_OUT_SEL, BLS_TO_DPI_RDMA1_TO_DSI); - regmap_write(config_regs, DISP_REG_CONFIG_DSI_SEL, - DSI_SEL_IN_RDMA); - regmap_write(config_regs, DISP_REG_CONFIG_DPI_SEL, - DPI_SEL_IN_BLS); } }