From patchwork Fri Jan 3 03:12:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 206232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E320C33C8C for ; Fri, 3 Jan 2020 03:13:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 211A022314 for ; Fri, 3 Jan 2020 03:13:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="NFBocSl0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727359AbgACDNp (ORCPT ); Thu, 2 Jan 2020 22:13:45 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:24834 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727400AbgACDMq (ORCPT ); Thu, 2 Jan 2020 22:12:46 -0500 X-UUID: 5d5fe0730d9840d1b936663316c08f5c-20200103 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=80Nbmr3xohHu1sbyZ9GY7LSVrpaKDxARTqzXy8B3cZE=; b=NFBocSl04BHo2A7ARre6WRnser38kwfaVuBHPikdvY2OscNyNOzZryepQKEnQJ3M2UKciqbcgDuKmThg+QrK9Vy5k6yD+whW2+x2AK7BGM5ahNUvj3fE89h486KWm6i2fZ0undBFGKs4z99RAZAF/jjFeBNQZjkc7WFBcHh392s=; X-UUID: 5d5fe0730d9840d1b936663316c08f5c-20200103 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1621327258; Fri, 03 Jan 2020 11:12:42 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 3 Jan 2020 11:12:15 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 3 Jan 2020 11:13:08 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger CC: David Airlie , Daniel Vetter , Mark Rutland , , , , , , Yongqiang Niu Subject: [RESEND PATCH v6 06/17] drm/mediatek: add private data for rdma1 to dpi0 connection Date: Fri, 3 Jan 2020 11:12:17 +0800 Message-ID: <1578021148-32413-7-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1578021148-32413-1-git-send-email-yongqiang.niu@mediatek.com> References: <1578021148-32413-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org the register offset and value will be different in future SOC, add private data for rdma1->dpi0 use case. Signed-off-by: Yongqiang Niu --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) -- 1.8.1.1.dirty diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index b279204..0015b35 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -170,6 +170,10 @@ struct mtk_ddp { struct mtk_mmsys_reg_data { u32 ovl0_mout_en; + u32 rdma1_sout_sel_in; + u32 rdma1_sout_dpi0; + u32 dpi0_sel_in; + u32 dpi0_sel_in_rdma1; }; static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { @@ -256,6 +260,10 @@ struct mtk_mmsys_reg_data { const struct mtk_mmsys_reg_data mt8173_mmsys_reg_data = { .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, + .rdma1_sout_sel_in = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, + .rdma1_sout_dpi0 = RDMA1_SOUT_DPI0, + .dpi0_sel_in = DISP_REG_CONFIG_DPI_SEL_IN, + .dpi0_sel_in_rdma1 = DPI0_SEL_IN_RDMA1, }; static unsigned int mtk_ddp_mout_en(const struct mtk_mmsys_reg_data *data, @@ -311,8 +319,8 @@ static unsigned int mtk_ddp_mout_en(const struct mtk_mmsys_reg_data *data, *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; value = RDMA1_SOUT_DSI3; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; + *addr = data->rdma1_sout_sel_in; + value =data->rdma1_sout_dpi0; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; value = RDMA1_SOUT_DPI1; @@ -349,8 +357,8 @@ static unsigned int mtk_ddp_sel_in(const struct mtk_mmsys_reg_data *data, *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; value = COLOR0_SEL_IN_OVL0; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; + *addr = data->dpi0_sel_in; + value = data->dpi0_sel_in_rdma1; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { *addr = DISP_REG_CONFIG_DPI_SEL_IN; value = DPI1_SEL_IN_RDMA1;