From patchwork Thu Aug 20 06:04:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 253585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96A36C433E1 for ; Thu, 20 Aug 2020 06:06:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 719BF214F1 for ; Thu, 20 Aug 2020 06:06:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="cxBhGK5O" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725859AbgHTGGh (ORCPT ); Thu, 20 Aug 2020 02:06:37 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:13121 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726852AbgHTGFw (ORCPT ); Thu, 20 Aug 2020 02:05:52 -0400 X-UUID: b756f09a9c244157af3ff069810e9104-20200820 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=81cl5lR8q9Xp2cMEda341JaElbb5a2VFUjfbX8XXRgM=; b=cxBhGK5O7qRZASx6HpHjPKVRm1kK7sxUoxnhMkLslim0cJK1Z2KUgGc6s3vNzz81WLqKsqqqLaipXrh4ygAyrWoFXyj1o2DSaJbamC+hmvk8yYims8+LU6WZNJcu7Iwih+JQe7vqoH5+wevJkp4/GAD+DRoPd1sakQO3WQ5/7I4=; X-UUID: b756f09a9c244157af3ff069810e9104-20200820 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 357292008; Thu, 20 Aug 2020 14:05:49 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 20 Aug 2020 14:05:47 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 20 Aug 2020 14:05:46 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger CC: David Airlie , Daniel Vetter , Mark Rutland , , , , , , Yongqiang Niu Subject: [PATCH v1 15/21] drm/mediatek: add color bypass shadow register function Date: Thu, 20 Aug 2020 14:04:12 +0800 Message-ID: <1597903458-8055-16-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1597903458-8055-1-git-send-email-yongqiang.niu@mediatek.com> References: <1597903458-8055-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org add color bypass shadow register function Signed-off-by: Yongqiang Niu --- drivers/gpu/drm/mediatek/mtk_disp_color.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 1.8.1.1.dirty diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c index 31918fa..83b075a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c @@ -17,6 +17,8 @@ #define DISP_COLOR_CFG_MAIN 0x0400 #define DISP_COLOR_START_MT2701 0x0f00 #define DISP_COLOR_START_MT8173 0x0c00 +#define DISP_COLOR_SHADOW_CTRL 0x0cb0 +#define COLOR_BYPASS_SHADOW BIT(0) #define DISP_COLOR_START(comp) ((comp)->data->color_offset) #define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) + 0x50) #define DISP_COLOR_HEIGHT(comp) (DISP_COLOR_START(comp) + 0x54) @@ -26,6 +28,7 @@ struct mtk_disp_color_data { unsigned int color_offset; + bool has_shadow; }; /** @@ -63,9 +66,21 @@ static void mtk_color_start(struct mtk_ddp_comp *comp) writel(0x1, comp->regs + DISP_COLOR_START(color)); } +static void mtk_color_bypass_shadow(struct mtk_ddp_comp *comp) +{ + struct mtk_disp_color *color = comp_to_color(comp); + + if (color->data->has_shadow) { + mtk_ddp_write_mask(NULL, COLOR_BYPASS_SHADOW, comp, + DISP_COLOR_SHADOW_CTRL, + COLOR_BYPASS_SHADOW); + } +} + static const struct mtk_ddp_comp_funcs mtk_disp_color_funcs = { .config = mtk_color_config, .start = mtk_color_start, + .bypass_shadow = mtk_color_bypass_shadow, }; static int mtk_disp_color_bind(struct device *dev, struct device *master,