From patchwork Thu Aug 20 06:04:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 253586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4237FC433DF for ; Thu, 20 Aug 2020 06:06:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 19BFA207DE for ; Thu, 20 Aug 2020 06:06:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="AQ51Iu74" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726875AbgHTGF4 (ORCPT ); Thu, 20 Aug 2020 02:05:56 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:35238 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726734AbgHTGFz (ORCPT ); Thu, 20 Aug 2020 02:05:55 -0400 X-UUID: 2b062464808e4ffca2481e893a1cafb8-20200820 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=36fnnR2AlgsNKVC8MFiMN1gZFhEDJZxQGNPYhMhVoAE=; b=AQ51Iu74p23vHnEjWOTCP6VTSfkCDMGpGyfqGsan9G08l0+SQ2ESc4QGsYqhtwZ1MaNAB2ffOgTxZs/43j0/PDHx2346PQ+vi658SuOfrjOYulNNSEBI9V87ic7KmVqQ+RQYJH8HudLVvR6LPmUDjked5IcdDvudR8vleqH2COE=; X-UUID: 2b062464808e4ffca2481e893a1cafb8-20200820 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1765723134; Thu, 20 Aug 2020 14:05:51 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 20 Aug 2020 14:05:48 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 20 Aug 2020 14:05:47 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger CC: David Airlie , Daniel Vetter , Mark Rutland , , , , , , Yongqiang Niu Subject: [PATCH v1 16/21] drm/mediatek: add ovl bypass shadow register function Date: Thu, 20 Aug 2020 14:04:13 +0800 Message-ID: <1597903458-8055-17-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1597903458-8055-1-git-send-email-yongqiang.niu@mediatek.com> References: <1597903458-8055-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org add ovl bypass shadow register function Signed-off-by: Yongqiang Niu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 1.8.1.1.dirty diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 03eaadb..fb0fe59 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -19,6 +19,9 @@ #define DISP_REG_OVL_INTEN 0x0004 #define OVL_FME_CPL_INT BIT(1) #define DISP_REG_OVL_INTSTA 0x0008 +#define OVL_EN BIT(0) +#define OVL_READ_WORK_REG BIT(20) +#define OVL_BYPASS_SHADOW BIT(22) #define DISP_REG_OVL_EN 0x000c #define DISP_REG_OVL_RST 0x0014 #define DISP_REG_OVL_ROI_SIZE 0x0020 @@ -62,6 +65,7 @@ struct mtk_disp_ovl_data { unsigned int gmc_bits; unsigned int layer_nr; bool fmt_rgb565_is_0; + bool has_shadow; }; /** @@ -126,6 +130,17 @@ static void mtk_ovl_stop(struct mtk_ddp_comp *comp) writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN); } +static void mtk_ovl_bypass_shadow(struct mtk_ddp_comp *comp) +{ + struct mtk_disp_ovl *ovl = comp_to_ovl(comp); + + if (ovl->data->has_shadow) { + mtk_ddp_write_mask(NULL, OVL_BYPASS_SHADOW, comp, + DISP_REG_OVL_EN, + OVL_BYPASS_SHADOW); + } +} + static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -318,6 +333,7 @@ static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp) .config = mtk_ovl_config, .start = mtk_ovl_start, .stop = mtk_ovl_stop, + .bypass_shadow = mtk_ovl_bypass_shadow, .enable_vblank = mtk_ovl_enable_vblank, .disable_vblank = mtk_ovl_disable_vblank, .supported_rotations = mtk_ovl_supported_rotations,