From patchwork Thu Aug 20 06:04:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 253588 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FBA1C433E3 for ; Thu, 20 Aug 2020 06:06:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0F13D207DE for ; Thu, 20 Aug 2020 06:06:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="czV+AgkW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726987AbgHTGGK (ORCPT ); Thu, 20 Aug 2020 02:06:10 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:23595 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726956AbgHTGGC (ORCPT ); Thu, 20 Aug 2020 02:06:02 -0400 X-UUID: b82de08971b946d3aed2258cd25444af-20200820 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Goa7JPmDFNuSu9rW6OSEL3atM2vBJYhtQ96kEWsc+t8=; b=czV+AgkWdFpfxcS6yTiw7gnojEFDXr76H0FMk16lX4LfI3gVSzSeUWPktHfWD0rJ9G/zb91L+ArqdT4GVhXa4z/X/7fiiT9btWMZF0LF2D334pExmyHahdnTYQHRSQfgEqIsYvFPu1f6PDOf0EkyVFyuBy6mditBW0r1HPL1rS4=; X-UUID: b82de08971b946d3aed2258cd25444af-20200820 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 2119355855; Thu, 20 Aug 2020 14:05:58 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 20 Aug 2020 14:05:56 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 20 Aug 2020 14:05:55 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger CC: David Airlie , Daniel Vetter , Mark Rutland , , , , , , Yongqiang Niu Subject: [PATCH v1 18/21] drm/mediatek: add dither bypass shadow register function Date: Thu, 20 Aug 2020 14:04:15 +0800 Message-ID: <1597903458-8055-19-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1597903458-8055-1-git-send-email-yongqiang.niu@mediatek.com> References: <1597903458-8055-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org add dither bypass shadow register function Signed-off-by: Yongqiang Niu --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 1.8.1.1.dirty diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 0c81253..315bd3a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -23,6 +23,9 @@ #define DISP_OD_INTSTA 0x000c #define DISP_OD_CFG 0x0020 #define DISP_OD_SIZE 0x0030 + +#define DITHER_REG(idx) (0x100 + (idx) * 4) +#define DITHER_BYPASS_SHADOW BIT(0) #define DISP_DITHER_5 0x0114 #define DISP_DITHER_7 0x011c #define DISP_DITHER_15 0x013c @@ -291,6 +294,13 @@ static void mtk_dither_stop(struct mtk_ddp_comp *comp) writel_relaxed(0x0, comp->regs + DISP_DITHER_EN); } +static void mtk_dither_bypass_shadow(struct mtk_ddp_comp *comp) +{ + mtk_ddp_write_mask(NULL, DITHER_BYPASS_SHADOW, comp, + DITHER_REG(0), + DITHER_BYPASS_SHADOW); +} + static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -368,6 +378,7 @@ static void mtk_postmask_stop(struct mtk_ddp_comp *comp) .config = mtk_dither_config, .start = mtk_dither_start, .stop = mtk_dither_stop, + .bypass_shadow = mtk_dither_bypass_shadow, }; static const struct mtk_ddp_comp_funcs ddp_gamma = {