From patchwork Thu Dec 17 09:25:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 345101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6148DC2D0E4 for ; Thu, 17 Dec 2020 09:27:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2EB26238EB for ; Thu, 17 Dec 2020 09:27:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725930AbgLQJ1J (ORCPT ); Thu, 17 Dec 2020 04:27:09 -0500 Received: from out28-101.mail.aliyun.com ([115.124.28.101]:34001 "EHLO out28-101.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726012AbgLQJ0s (ORCPT ); Thu, 17 Dec 2020 04:26:48 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.09333897|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.00966935-0.000308897-0.990022; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047203; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=13; RT=13; SR=0; TI=SMTPD_---.J8ErjJ0_1608197156; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.J8ErjJ0_1608197156) by smtp.aliyun-inc.com(10.147.40.26); Thu, 17 Dec 2020 17:26:03 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: sboyd@kernel.org, robh+dt@kernel.org Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, mturquette@baylibre.com, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, yanfei.li@ingenic.com, sihui.liu@ingenic.com, sernia.zhou@foxmail.com, paul@crapouillou.net Subject: [PATCH v3 1/5] clk: JZ4780: Add function for disable the second core. Date: Thu, 17 Dec 2020 17:25:49 +0800 Message-Id: <1608197153-84915-2-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1608197153-84915-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1608197153-84915-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add "jz4780_core1_disable()" for disable the second core of JZ4780, prepare for later commits. Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Paul Cercueil --- Notes: v1->v2: Add Paul Cercueil's Reviewed-by. v2->v3: No change. drivers/clk/ingenic/jz4780-cgu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index 0268d23..dcca74e 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -252,8 +252,29 @@ static int jz4780_core1_enable(struct clk_hw *hw) return 0; } +static void jz4780_core1_disable(struct clk_hw *hw) +{ + struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); + struct ingenic_cgu *cgu = ingenic_clk->cgu; + unsigned long flags; + u32 lcr, clkgr1; + + spin_lock_irqsave(&cgu->lock, flags); + + lcr = readl(cgu->base + CGU_REG_LCR); + lcr |= LCR_PD_SCPU; + writel(lcr, cgu->base + CGU_REG_LCR); + + clkgr1 = readl(cgu->base + CGU_REG_CLKGR1); + clkgr1 |= CLKGR1_CORE1; + writel(clkgr1, cgu->base + CGU_REG_CLKGR1); + + spin_unlock_irqrestore(&cgu->lock, flags); +} + static const struct clk_ops jz4780_core1_ops = { .enable = jz4780_core1_enable, + .disable = jz4780_core1_disable, }; static const s8 pll_od_encoding[16] = {