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[1/3] dt-bindings: cpufreq: sama7g5-cpufreq: add dt bindings documentation

Message ID 1609842147-8161-2-git-send-email-claudiu.beznea@microchip.com
State New
Headers show
Series cpufreq: sama7g5: add support for sama7g5 | expand

Commit Message

Claudiu Beznea Jan. 5, 2021, 10:22 a.m. UTC 
Add DT bindings documentation for SAMA7G5 CPUFreq driver.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 .../bindings/cpufreq/cpufreq-sama7g5.yaml          | 80 ++++++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-sama7g5.yaml
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Patch

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-sama7g5.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-sama7g5.yaml
new file mode 100644
index 000000000000..e8185a614035
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-sama7g5.yaml
@@ -0,0 +1,80 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/cpufreq-sama7g5.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SAMA7G5's CPUFreq device tree bindings
+
+maintainers:
+  - Claudiu Beznea <claudiu.beznea@microchip.com>
+
+properties:
+  clocks:
+    items:
+      - description: The clock feeding the CPU
+      - description: The clock sharing the PLL and prescaller with CPU clock
+
+  clock-names:
+    items:
+      - const: cpu
+      - const: mck
+
+  operating-points-v2:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to OPP table
+
+  cpu-supply:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to CPU's voltage regulator
+
+required:
+  - clocks
+  - clock-names
+  - operating-points-v2
+  - cpu-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/at91.h>
+    cpu_opp_table: opp-table {
+            compatible = "operating-points-v2";
+
+            opp-600000000 {
+                    opp-hz = /bits/ 64 <600000000>;
+                    opp-microvolt = <1125000 1050000 1225000>;
+                    clock-latency-ns = <50000>;
+            };
+
+            opp-800000000 {
+                    opp-hz = /bits/ 64 <800000000>;
+                    opp-microvolt = <1175000 1125000 1225000>;
+                    clock-latency-ns = <50000>;
+            };
+
+            opp-1000000000 {
+                    opp-hz = /bits/ 64 <1000000000>;
+                    opp-microvolt = <1275000 1225000 1300000>;
+                    clock-latency-ns = <50000>;
+            };
+    };
+
+  - |
+    cpus {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            cpu0: cpu@0 {
+                    device_type = "cpu";
+                    compatible = "arm,cortex-a7";
+                    reg = <0x0>;
+                    clocks = <&pmc PMC_TYPE_CORE PMC_CPU>, <&pmc PMC_TYPE_CORE PMC_MCK>;
+                    clock-names = "cpu", "mck";
+                    operating-points-v2 = <&cpu_opp_table>;
+                    cpu-supply = <&vddcpu>;
+            };
+    };