From patchwork Thu Aug 12 07:41:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajesh Patil X-Patchwork-Id: 496209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86EB1C04FE3 for ; Thu, 12 Aug 2021 07:42:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6202A610A4 for ; Thu, 12 Aug 2021 07:42:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234901AbhHLHnR (ORCPT ); Thu, 12 Aug 2021 03:43:17 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:34292 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234888AbhHLHnQ (ORCPT ); Thu, 12 Aug 2021 03:43:16 -0400 Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 12 Aug 2021 00:42:52 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 12 Aug 2021 00:42:50 -0700 X-QCInternal: smtphost Received: from rajpat-linux.qualcomm.com ([10.206.21.0]) by ironmsg01-blr.qualcomm.com with ESMTP; 12 Aug 2021 13:12:20 +0530 Received: by rajpat-linux.qualcomm.com (Postfix, from userid 2344945) id A21B221508; Thu, 12 Aug 2021 13:12:18 +0530 (IST) From: Rajesh Patil To: Andy Gross , Bjorn Andersson , Rob Herring Cc: swboyd@chromium.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, rnayak@codeaurora.org, saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com, skakit@codeaurora.org, Rajesh Patil Subject: [PATCH V5 5/7] arm64: dts: sc7280: Configure debug uart for sc7280-idp Date: Thu, 12 Aug 2021 13:11:16 +0530 Message-Id: <1628754078-29779-6-git-send-email-rajpat@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1628754078-29779-1-git-send-email-rajpat@codeaurora.org> References: <1628754078-29779-1-git-send-email-rajpat@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Configure uart5 as debug uart and split the pinctrl functions to match with SoC dt. Signed-off-by: Rajesh Patil --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index c41c2d0..53993b3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -254,6 +254,7 @@ }; &uart5 { + compatible = "qcom,geni-debug-uart"; status = "okay"; }; @@ -311,18 +312,14 @@ bias-pull-up; }; -&qup_uart5_default { - tx { - pins = "gpio46"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart5_tx { + drive-strength = <2>; + bias-disable; +}; - rx { - pins = "gpio47"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart5_rx { + drive-strength = <2>; + bias-pull-up; }; &sdc1_on {