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Sat, 29 Jan 2022 08:41:57 -0800 From: Akhil R To: , , , , , , , , , , , CC: Subject: [PATCH v17 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Date: Sat, 29 Jan 2022 22:10:50 +0530 Message-ID: <1643474453-32619-2-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1643474453-32619-1-git-send-email-akhilrajeev@nvidia.com> References: <1643474453-32619-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f631388c-8528-4822-64d2-08d9e346473c X-MS-TrafficTypeDiagnostic: DM5PR12MB2360:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JGJ/hfNf3NdKe2qbRfhWPrJMWYfpA304iGn00KNd2sKgG+tqAv+sgraREK03f0rlCVVN4x+OK2JVUPrGRPQLrrdnby79Fn8nvZeii18XGGY26oLMb9OkoCkMaqYv1zjtnis/oNZzN+jMqYZ0hNgFGjsUkRJh4PkKveeEdP45a5l2WB4NGcKAfpkCpdQ45pDtV4p9By1i/1g8UY3aTHUwduT2bnO5Kx9bV+Lc6uxlkbt7gxNN8z+X2Pc0lPruMFRSAxtiSNnRJlKNKH3wtgSCUK2H9sI95xJMZduSSvCVfSB0w+9g4/yuTiClKzl53mA87Bic/WSRttewBUuhzZ/qbW9wmKynLhKLdMJkzaGcseAXKaZDMZMXO8QrhfBbs1bJw3Wd8Q8BpYwLUH3sqGrHXcTgL8MCEuSZkIVJ8O59zJ/Lryz8YBEfJB2NON3Vb+0XPou6Il5Jq0vBXgSFWfwcMNNNZlxUOg/NQXP6Vi7VwJwYZgExn/FrngM6Mjd6bCpIR59rRjORbon9RGkst03r9Vliv7effHtE1+lAa/TN0PddaS4BjX9RzLMecMkaKcnDsWI5m9BktPpHKPP72D5jd9Esc3FPDTCuaMuGp54+c4eCxcINjhq1GNJbZjSSt0e6BLY5rnbyThz0wUq4rvNBukaaLzAwihUw772kNW6WBIQhblmvVFsehM1JW8Vmwt77lWBMGFxFa5FYGDDQpoNfFxXfMmmqWqd9psBkmmeWo0JP8ms+UjIS9Xg+0xnnfGmB412gn0mhcCinYCttJ57WUODiUDFSRJuj33CxK5YYa9wsivJKmnmC9wQR2289HzKp1P9eC7vrd9Qvufaz5tV62xaowO1AM7mc+BrqC7OeOWzL0i/iwHth0OWJoWlF1c1ohb4B08T7kM2m7e+Cjw/upg== X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(186003)(81166007)(2616005)(36756003)(26005)(7696005)(2906002)(40460700003)(107886003)(921005)(36860700001)(356005)(5660300002)(4326008)(6666004)(47076005)(336012)(8936002)(426003)(508600001)(70206006)(82310400004)(110136005)(316002)(70586007)(8676002)(966005)(83380400001)(86362001)(2101003)(83996005)(36900700001)(20210929001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2022 16:42:03.0742 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f631388c-8528-4822-64d2-08d9e346473c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2360 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding document for Nvidia Tegra GPCDMA controller. Signed-off-by: Rajesh Gumasta Signed-off-by: Akhil R Reviewed-by: Jon Hunter Reviewed-by: Rob Herring --- .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 110 +++++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml new file mode 100644 index 0000000..9dd1476 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings + +description: | + The Tegra General Purpose Central (GPC) DMA controller is used for faster + data transfers between memory to memory, memory to device and device to + memory. + +maintainers: + - Jon Hunter + - Rajesh Gumasta + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + oneOf: + - const: nvidia,tegra186-gpcdma + - items: + - const: nvidia,tegra194-gpcdma + - const: nvidia,tegra186-gpcdma + + "#dma-cells": + const: 1 + + reg: + maxItems: 1 + + interrupts: + description: + Should contain all of the per-channel DMA interrupts in + ascending order with respect to the DMA channel index. + minItems: 1 + maxItems: 31 + + resets: + maxItems: 1 + + reset-names: + const: gpcdma + + iommus: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + - resets + - reset-names + - "#dma-cells" + - iommus + +additionalProperties: false + +examples: + - | + #include + #include + #include + + dma-controller@2600000 { + compatible = "nvidia,tegra186-gpcdma"; + reg = <0x2600000 0x210000>; + resets = <&bpmp TEGRA186_RESET_GPCDMA>; + reset-names = "gpcdma"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + }; +...