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Mon, 21 Nov 2022 10:43:16 -0600 From: Lizhi Hou To: , , , , , CC: Lizhi Hou , , , , , , , Subject: [RESEND PATCH RFC V4 3/3] PCI: Add PCI quirks to generate device tree node for Xilinx Alveo U50 Date: Mon, 21 Nov 2022 08:43:04 -0800 Message-ID: <1669048984-56394-4-git-send-email-lizhi.hou@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1669048984-56394-1-git-send-email-lizhi.hou@amd.com> References: <1669048984-56394-1-git-send-email-lizhi.hou@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT055:EE_|MW4PR12MB6876:EE_ X-MS-Office365-Filtering-Correlation-Id: b53e4737-aa55-478d-bf90-08dacbdf7e27 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: c2SRC6cXPmWJL2P78fPjrvq+7BzHrIncOSANufEQEK4ogCDq9mAkZQy6aUxdS2n/KNHdSLA091eQMrrHBCC93x7vgmDFzHDaLZ2wfDODh0QLpnTPb/gajdQPMgKGEyE064WHwO62jhgIcG32Z2YKzMT3GL32LlPj6/cwY9bpUSRleDffthOL5TAWJSnM88wYB4k/kHTKEhBhBEOlZAGRD1xflyo/osIO4BEdHkJG5IiH2jKblZltQauh3L715Bo8DSdxsONE8gX0cjKB63Y+0Ntgo3hx+msS+dK7L1Pq4Tn7vKBnNAbLKHoFYBgpp5mCSubE7fn1eyrdVI0FKF6Y7q8/LjF2Ozqq0mxiCrZVUypaTFPb7Qgvx+mi9IvkEnaqOXWy2yeR9mhGUlalqA0OcSx7NEdSXnDpgRLX2lvKfHEmOuMFzwSTxuBUP4WvKwiZJyeBruVZPmnTqkiKO6F/74EIbh94gt/HSzOmNvuYXLm290SCR6yzm/gMh5utKkTCTEBMazgNT0r3dqNhYtKd2SwXKD0/8ASFHQq14XF0S35wZxO2XiY1bCpsQOPKHBOHXB0c3uwQvxulJbfo/P1h4wOxiWdKH93UgIfJZPwuzxPJoSv0OmeR0b1VGgD5I7kWeLBJZaxJeM7UZqhAjpRR6xFnFcWjI85CGT51SHYANkTq+Y22zCqJ57Ih/gmAxGAZCimespkHnRo0IX1YfQF3RDIM31TexRMnE64Kpn7muOw= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(396003)(346002)(136003)(376002)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(36756003)(478600001)(5660300002)(44832011)(336012)(47076005)(40460700003)(70586007)(4326008)(8676002)(426003)(70206006)(26005)(54906003)(316002)(110136005)(2616005)(8936002)(82310400005)(356005)(36860700001)(81166007)(82740400003)(41300700001)(186003)(2906002)(40480700001)(86362001)(6666004)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2022 16:43:18.0557 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b53e4737-aa55-478d-bf90-08dacbdf7e27 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6876 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Xilinx Alveo U50 PCI card exposes multiple hardware peripherals on its PCI BAR. The card firmware provides a flattened device tree to describe the hardware peripherals on its BARs. This allows U50 driver to load the flattened device tree and generate the device tree node for hardware peripherals underneath. To generate device tree node for U50 card, added PCI quirks to call of_pci_make_dev_node() for U50. Signed-off-by: Lizhi Hou Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Reviewed-by: Brian Xu --- drivers/pci/quirks.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 4944798e75b5..5d76932f59ec 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5956,3 +5956,14 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); #endif + +/* + * For PCI device which have multiple downstream devices, its driver may use + * a flattened device tree to describe the downstream devices. + * To overlay the flattened device tree, the PCI device and all its ancestor + * devices need to have device tree nodes on system base device tree. Thus, + * before driver probing, it might need to add a device tree node as the final + * fixup. + */ +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);