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Fri, 28 Jul 2023 12:07:03 -0500 Received: from xsjlizhih40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Fri, 28 Jul 2023 12:07:02 -0500 From: Lizhi Hou To: , , , CC: Lizhi Hou , , , Subject: [PATCH V12 3/5] PCI: Add quirks to generate device tree node for Xilinx Alveo U50 Date: Fri, 28 Jul 2023 10:06:56 -0700 Message-ID: <1690564018-11142-4-git-send-email-lizhi.hou@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1690564018-11142-1-git-send-email-lizhi.hou@amd.com> References: <1690564018-11142-1-git-send-email-lizhi.hou@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT112:EE_|IA1PR12MB6331:EE_ X-MS-Office365-Filtering-Correlation-Id: 07cede8a-8736-4c7b-f901-08db8f8d118b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /DZnJOtALtgKYB0YxUjDt2KTiR03XL7meyqPTeuwo84FAlN68xgDxXKrVXpwJ9ZlsTmTg+94uEgUYm8z18Gz0fNaxyD+v/+6+DncD4l7kkd7y8U9ZNE2ZqSZ5AkLkwY3abp0T7TZb55O9LaVeaCGUa0E2VYOAWq05s1vR1FFlTZlDucGJumKTFTQCAVHPQ/yFbMofLdI0IU5sZCMdJU1ndlgTbm1jlzjQhoisELx3ZpN9ojRF8Zs9A7BVsWlyXo/XmA1uPZ4O5wZH95tU+r7D/0dl9G9wxn9rSMuAgI2xavtIs1eTlqglKG6NTANf9uUD56YW0AXuWGiuwfHbiMu0MrAsT0eR8bWLUT0/vvg+4iVIbeOMmnUJXp5EvygeSHSQ45J+yf2BKyJRhzoUYJ+S2vP//zVgjFO713TWjlhmxBLVeZeUYm8sjpej6ZobB2dalnTQzrc+oJybQ/NP+tb/VxdxFIch1ppGRfTaGxVj9eqzzSEHoCJ0Df/dGti/BjVAdKR9ZaT4bT5W+ZqyMLSJr3B0DKV3kVp2LBdRKVyYQN6QxDthfZu35bMUUO8sGP5eASn1fE1HaIZLAkMF9L0SXgnMikzQzejTShpBzdEIkoWohYfeDS4T4PZZchv5r5riryfT+FkP7QimgHJuabAWMAhBknu1wXK/AHUtjAC3uJKOCYdIzAcdxiKvNNSlN/PO7ZZOGVveN1/pjGKjF7VTLgT/gFqg0AQat3Aqv/5YK/ZzfI8RWHD0aJkrvSgWaw5coa8OYpc6yIRphw5nAOxhA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(39860400002)(376002)(136003)(396003)(346002)(82310400008)(451199021)(36840700001)(40470700004)(46966006)(2906002)(316002)(8936002)(8676002)(40460700003)(5660300002)(44832011)(41300700001)(36756003)(40480700001)(86362001)(6666004)(426003)(81166007)(54906003)(82740400003)(478600001)(356005)(26005)(186003)(336012)(110136005)(2616005)(70206006)(70586007)(36860700001)(47076005)(4326008)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jul 2023 17:07:05.0135 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 07cede8a-8736-4c7b-f901-08db8f8d118b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT112.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6331 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Xilinx Alveo U50 PCI card exposes multiple hardware peripherals on its PCI BAR. The card firmware provides a flattened device tree to describe the hardware peripherals on its BARs. This allows U50 driver to load the flattened device tree and generate the device tree node for hardware peripherals underneath. To generate device tree node for U50 card, add PCI quirks to call of_pci_make_dev_node() for U50. Acked-by: Bjorn Helgaas Signed-off-by: Lizhi Hou --- drivers/pci/quirks.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 321156ca273d..6c0e7b6bbdd1 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -6138,3 +6138,14 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); #endif + +/* + * For a PCI device with multiple downstream devices, its driver may use + * a flattened device tree to describe the downstream devices. + * To overlay the flattened device tree, the PCI device and all its ancestor + * devices need to have device tree nodes on system base device tree. Thus, + * before driver probing, it might need to add a device tree node as the final + * fixup. + */ +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);