From patchwork Fri Sep 22 10:08:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 114014 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3155782qgf; Fri, 22 Sep 2017 04:10:53 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDSqI2GcvH3ilfmawK9VeifRbzJIHKhyN9hqkTAjjiCdswXenOyY1e/luwIMm95UmH2AxaL X-Received: by 10.99.160.65 with SMTP id u1mr8977507pgn.227.1506078653881; Fri, 22 Sep 2017 04:10:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506078653; cv=none; d=google.com; s=arc-20160816; b=lPvgdHWp4ksZXXXz80/Po0XJSUi/wmQNjczaV6WDbqjs/KKAmg6QQYiukKEpmo+Qdz Zijkrygp70HzQlUiC1EyW/Bt72UBGJ1gM5ipezYaUP8YBVE00XYj1PTcx9FC5MD7lbpe vLW2fBpd+zTFjQAXt2lmMihD9D+7knSb1xTHuigoK8by79L2OjzO2vBBZZNq8d94EoUp JX24BxwFEWBBgL1MQfTeb+rNg0IZUbrVcOSwSr1CMbt1j9DCNfmcQk10fXTvKz3OGtf2 lQVhy0skP0YIwuxeke2bWmjgv8JvBJlOve7udCkV2ePjyEunZAF2goQi4p0g26f++vJf s1vQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=CvTI54KKFy5RI+czD9Y3gEZ8irTHvVFQvfXN+cvWokw=; b=Eb2zEyHwO/3rPvJArGnVA3ofdqC0jYPMzSsdowc2r7tzfv3S5XAo1H0uf3m+/CMTGp /nASMi1AKQ1wWMnP4nUQBxAMvSE/RBuFFDGhL1l0sgu1ByXuePGpkRcvaDieKEhXz+HJ rPfGRSWKIcgSu73PphAi7jQkb6qqUazrZ43zNtm6sRAsijvftRxgQthT8Ohcvq/mb+ct Bnw2sz8ZbWv/JMaRrO/ienNHrubE0Qw/Ia3N6ytLiJz6VMQginHSc/GmFPK21zZ1H25R sXFFiPk5F8rBFxGJZ/xreIOvH9wYf0ZADbkDfmbT7H5oCGYMgOKNR8j+YutKNUGxaF3A qpAw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o123si2543154pfb.174.2017.09.22.04.10.53; Fri, 22 Sep 2017 04:10:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751985AbdIVLKw (ORCPT + 6 others); Fri, 22 Sep 2017 07:10:52 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:58788 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751919AbdIVLKv (ORCPT ); Fri, 22 Sep 2017 07:10:51 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id CCC05209DB; Fri, 22 Sep 2017 13:10:48 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id A1201208ED; Fri, 22 Sep 2017 13:10:48 +0200 (CEST) From: Maxime Ripard To: Mauro Carvalho Chehab , Mark Rutland , Rob Herring Cc: Laurent Pinchart , linux-media@vger.kernel.org, devicetree@vger.kernel.org, Cyprian Wronka , Richard Sproul , Alan Douglas , Steve Creaney , Thomas Petazzoni , Boris Brezillon , =?utf-8?q?Niklas_S=C3=B6derlund?= , Hans Verkuil , Sakari Ailus , Benoit Parrot , nm@ti.com, Maxime Ripard Subject: [PATCH v4 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 RX Device Tree bindings Date: Fri, 22 Sep 2017 12:08:22 +0200 Message-Id: <20170922100823.18184-2-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170922100823.18184-1-maxime.ripard@free-electrons.com> References: <20170922100823.18184-1-maxime.ripard@free-electrons.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to 4 CSI-2 lanes, and can route the frames to up to 4 streams, depending on the hardware implementation. It can operate with an external D-PHY, an internal one or no D-PHY at all in some configurations. Acked-by: Rob Herring Acked-by: Benoit Parrot Acked-by: Sakari Ailus Reviewed-by: Laurent Pinchart Signed-off-by: Maxime Ripard --- .../devicetree/bindings/media/cdns,csi2rx.txt | 97 ++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.txt -- 2.13.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt new file mode 100644 index 000000000000..e9c30f964a96 --- /dev/null +++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt @@ -0,0 +1,97 @@ +Cadence MIPI-CSI2 RX controller +=============================== + +The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI +lanes in input, and 4 different pixel streams in output. + +Required properties: + - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible + - reg: base address and size of the memory mapped region + - clocks: phandles to the clocks driving the controller + - clock-names: must contain: + * sys_clk: main clock + * p_clk: register bank clock + * pixel_if[0-3]_clk: pixel stream output clock, one for each stream + implemented in hardware, between 0 and 3 + +Optional properties: + - phys: phandle to the external D-PHY, phy-names must be provided + - phy-names: must contain dphy, if the implementation uses an + external D-PHY + +Required subnodes: + - ports: A ports node with one port child node per device input and output + port, in accordance with the video interface bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + port nodes numbered as follows. + + Port Description + ----------------------------- + 0 CSI-2 input + 1 Stream 0 output + 2 Stream 1 output + 3 Stream 2 output + 4 Stream 3 output + + The stream output port nodes are optional if they are not connected + to anything at the hardware level or implemented in the design. + +Example: + +csi2rx: csi-bridge@0d060000 { + compatible = "cdns,csi2rx"; + reg = <0x0d060000 0x1000>; + clocks = <&byteclock>, <&byteclock> + <&coreclock>, <&coreclock>, + <&coreclock>, <&coreclock>; + clock-names = "sys_clk", "p_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi2rx_in_sensor: endpoint { + remote-endpoint = <&sensor_out_csi2rx>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + csi2rx_out_grabber0: endpoint { + remote-endpoint = <&grabber0_in_csi2rx>; + }; + }; + + port@2 { + reg = <2>; + + csi2rx_out_grabber1: endpoint { + remote-endpoint = <&grabber1_in_csi2rx>; + }; + }; + + port@3 { + reg = <3>; + + csi2rx_out_grabber2: endpoint { + remote-endpoint = <&grabber2_in_csi2rx>; + }; + }; + + port@4 { + reg = <4>; + + csi2rx_out_grabber3: endpoint { + remote-endpoint = <&grabber3_in_csi2rx>; + }; + }; + }; +};