From patchwork Sat Feb 10 02:41:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 127893 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1187735ljc; Fri, 9 Feb 2018 18:43:06 -0800 (PST) X-Google-Smtp-Source: AH8x224ewSH9msUpetHc/fql9km2zmEcqj3zQXmo3f1ShTocSA8bLLd2S4zAutJpI1PqAO1S0wax X-Received: by 10.98.171.12 with SMTP id p12mr4806428pff.71.1518230586686; Fri, 09 Feb 2018 18:43:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518230586; cv=none; d=google.com; s=arc-20160816; b=K60FvFPhJHvuYqOXilU7Rs1K9vnUq8yHVLN3DHfl3WmI4+7BalscJYlSmJiE2jH3mk YzzfZw+qv5mBkyFig/pB+/hWM+SJcWkMUj2cIdfugso9U5EB5NalutXS7GEKVTzMII3L UmkjIRYd3YOsmJ6tjOv1gJkHtYhat8UXnLHgEXY2vR4rNiBUKoNdrSiphuF70oQDxEg7 yeepsxfx/t+mCBuMbGEpaPP1bOVLqf3jA63SXM+yr4L/9Irz05Ix/RSMGUn52puhnM+Z HpFStHzIy7ge319bgfk70QovqLula/yZJnhM5K93G6XCz1B5CAQmoE+LQ8ElY2+GZxjF g+Zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=B0SwcckNECcfj6DufImMXDfQ1ynM/Y5XM6bPs4+F1JY=; b=zhQuDI7bjS29LPD3EavBqZpYG64LpnYFNKnTt96C9+Rsqqi7yp3giiV/yLIx3zweh+ CifLQHnyq7sQih5xLQ320yaLh0QjlNb1NlX5C8Wj/z00KcGDXxtklIHwm6A3l3ElbmlT BMDaoq9eNqXbq07EUwC7QY1r3/iosyai1UZd2oaaVtmdGMXUgi1WAcdCpB2zz2A2DGcx 3JmFiAXQ47QGUGQ3SednRGYzGTJ3n+wV72gfMqR5REvlsgDi1O1IhraNJFMyzqN2U5ds et0kbnV0kPtZC+quAgbK34p3HL37cfycgoBneuXhpVWxv1VEaFVhX/2/KEgEWT2obply hhPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hlCYiedQ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n12si2180061pgs.141.2018.02.09.18.43.06; Fri, 09 Feb 2018 18:43:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hlCYiedQ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752469AbeBJCnE (ORCPT + 6 others); Fri, 9 Feb 2018 21:43:04 -0500 Received: from mail-pg0-f65.google.com ([74.125.83.65]:46136 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752481AbeBJCnB (ORCPT ); Fri, 9 Feb 2018 21:43:01 -0500 Received: by mail-pg0-f65.google.com with SMTP id a11so4849183pgu.13 for ; Fri, 09 Feb 2018 18:43:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZWdaozZYi4NnanLzMhOZBl7oIr/1UUReVz54XKaaEeI=; b=hlCYiedQfQ2G+iqX4Q3ZMxUIyZGo5EkLOQ1DQ0jY1HOOZotST3VhKLpcH+PxOVjMi7 Mls/B3AmBteJFJFt7SxJPLWwsVW/1bm/tc8XRS75ZM63xez4x3nLXSe1hxieCNmOUKYW 9QyTKtTBCyxGRkQI8DsRk6Y6YGPDRZ7xcKr30= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZWdaozZYi4NnanLzMhOZBl7oIr/1UUReVz54XKaaEeI=; b=Td7AYGAgRHHSYr81NtZv0LysYzZHw2xHEEnzmhylSolAPKOdq0xUlA2t6h+ttzmnn9 6jFHoSYNxWStlkZ5hQzX4/JxWjTN34zHIe9o919zQalTOM7J76QUvciBnwIksDIjhEZW W1Yjq/ri7T7qNNQR+t1bH4L7AkLfVH6LaZ3VObyRwKbgZSu16FcOdtRPk3/x10tjUX4n oFI4s6dMqvmdauxvK6G3Er4pDRD/JiChK1euqmPPpE8nTB7s/g2qksxqOZ/MecBz0CCU bQXYRa0VQoR/kNyxHdjHvwCuaNF6uw2AufPyFe1QM68wU71CSzlCU4h4lq8Ghkmby1sE VgKg== X-Gm-Message-State: APf1xPCC5tmjdeWo/nhwEflfmUwCyu/YCstHT9fITxOLCEEX9TM2RM7v VqkULe3hCxndMSgP5UVgefzG3049zFKk X-Received: by 10.99.181.72 with SMTP id u8mr3980920pgo.205.1518230580460; Fri, 09 Feb 2018 18:43:00 -0800 (PST) Received: from localhost.localdomain ([2405:204:7185:1f8f:fdb9:648e:14d3:8b97]) by smtp.gmail.com with ESMTPSA id z6sm7883286pgu.49.2018.02.09.18.42.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Feb 2018 18:42:59 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@codeaurora.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, viresh.kumar@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 09/11] clk: actions: Add composite clock support Date: Sat, 10 Feb 2018 08:11:18 +0530 Message-Id: <20180210024120.27503-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180210024120.27503-1-manivannan.sadhasivam@linaro.org> References: <20180210024120.27503-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for Actions Semi composite clock. This clock consists of gate, mux, divider and factor clocks. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-composite.c | 155 ++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-composite.h | 101 +++++++++++++++++++++++ 3 files changed, 257 insertions(+) create mode 100644 drivers/clk/actions/owl-composite.c create mode 100644 drivers/clk/actions/owl-composite.h -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index 994357fa560b..53431aef6e9c 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -5,3 +5,4 @@ clk-owl-y += owl-gate.o clk-owl-y += owl-mux.o clk-owl-y += owl-divider.o clk-owl-y += owl-factor.o +clk-owl-y += owl-composite.o diff --git a/drivers/clk/actions/owl-composite.c b/drivers/clk/actions/owl-composite.c new file mode 100644 index 000000000000..04fe1645a60d --- /dev/null +++ b/drivers/clk/actions/owl-composite.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL composite clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include + +#include "owl-composite.h" + +static u8 owl_comp_get_parent(struct clk_hw *hw) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_mux_helper_get_parent(&comp->common, &comp->mux_hw); +} + +static int owl_comp_set_parent(struct clk_hw *hw, u8 index) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_mux_helper_set_parent(&comp->common, &comp->mux_hw, index); +} + +static void owl_comp_disable(struct clk_hw *hw) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + struct owl_clk_common *common = &comp->common; + + clk_gate_set(common, &comp->gate_hw, false); +} + +static int owl_comp_enable(struct clk_hw *hw) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + struct owl_clk_common *common = &comp->common; + + clk_gate_set(common, &comp->gate_hw, true); + + return 0; +} + +static int owl_comp_is_enabled(struct clk_hw *hw) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + struct owl_clk_common *common = &comp->common; + + return clk_is_enabled(common, &comp->gate_hw); +} + +static long owl_comp_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw, + rate, parent_rate); +} + +static unsigned long owl_comp_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_divider_helper_recalc_rate(&comp->common, &comp->rate.div_hw, + parent_rate); +} + +static int owl_comp_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_divider_helper_set_rate(&comp->common, &comp->rate.div_hw, + rate, parent_rate); +} + +static long owl_comp_fact_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_factor_helper_round_rate(&comp->common, + &comp->rate.factor_hw, + rate, parent_rate); +} + +static unsigned long owl_comp_fact_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_factor_helper_recalc_rate(&comp->common, + &comp->rate.factor_hw, + parent_rate); +} + +static int owl_comp_fact_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_factor_helper_set_rate(&comp->common, + &comp->rate.factor_hw, + rate, parent_rate); +} + +const struct clk_ops owl_comp_div_ops = { + /* mux_ops */ + .get_parent = owl_comp_get_parent, + .set_parent = owl_comp_set_parent, + + /* gate_ops */ + .disable = owl_comp_disable, + .enable = owl_comp_enable, + .is_enabled = owl_comp_is_enabled, + + /* div_ops */ + .round_rate = owl_comp_div_round_rate, + .recalc_rate = owl_comp_div_recalc_rate, + .set_rate = owl_comp_div_set_rate, +}; + + +const struct clk_ops owl_comp_fact_ops = { + /* mux_ops */ + .get_parent = owl_comp_get_parent, + .set_parent = owl_comp_set_parent, + + /* gate_ops */ + .disable = owl_comp_disable, + .enable = owl_comp_enable, + .is_enabled = owl_comp_is_enabled, + + /* fact_ops */ + .round_rate = owl_comp_fact_round_rate, + .recalc_rate = owl_comp_fact_recalc_rate, + .set_rate = owl_comp_fact_set_rate, +}; + +const struct clk_ops owl_comp_pass_ops = { + /* mux_ops */ + .get_parent = owl_comp_get_parent, + .set_parent = owl_comp_set_parent, + + /* gate_ops */ + .disable = owl_comp_disable, + .enable = owl_comp_enable, + .is_enabled = owl_comp_is_enabled, +}; diff --git a/drivers/clk/actions/owl-composite.h b/drivers/clk/actions/owl-composite.h new file mode 100644 index 000000000000..386a93ac951e --- /dev/null +++ b/drivers/clk/actions/owl-composite.h @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL composite clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_COMPOSITE_H_ +#define _OWL_COMPOSITE_H_ + +#include "owl-common.h" +#include "owl-mux.h" +#include "owl-gate.h" +#include "owl-factor.h" +#include "owl-divider.h" + +union owl_rate { + struct owl_divider_hw div_hw; + struct owl_factor_hw factor_hw; +}; + +struct owl_composite { + struct owl_mux_hw mux_hw; + struct owl_gate_hw gate_hw; + union owl_rate rate; + struct owl_clk_common common; +}; + +#define OWL_COMP_DIV(_struct, _name, _parent, \ + _mux, _gate, _div, _flags) \ + struct owl_composite _struct = { \ + .mux_hw = _mux, \ + .gate_hw = _gate, \ + .rate.div_hw = _div, \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parent, \ + &owl_comp_div_ops,\ + _flags), \ + }, \ + } + +#define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \ + _gate, _div, _flags) \ + struct owl_composite _struct = { \ + .gate_hw = _gate, \ + .rate.div_hw = _div, \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT(_name, \ + _parent, \ + &owl_comp_div_ops,\ + _flags), \ + }, \ + } + +#define OWL_COMP_FACTOR(_struct, _name, _parent, \ + _mux, _gate, _factor, _flags) \ + struct owl_composite _struct = { \ + .mux_hw = _mux, \ + .gate_hw = _gate, \ + .rate.factor_hw = _factor, \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parent, \ + &owl_comp_fact_ops,\ + _flags), \ + }, \ + } + +#define OWL_COMP_PASS(_struct, _name, _parent, \ + _mux, _gate, _flags) \ + struct owl_composite _struct = { \ + .mux_hw = _mux, \ + .gate_hw = _gate, \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parent, \ + &owl_comp_pass_ops,\ + _flags), \ + }, \ + } + +static inline struct owl_composite *hw_to_owl_comp(const struct clk_hw *hw) +{ + struct owl_clk_common *common = hw_to_owl_clk_common(hw); + + return container_of(common, struct owl_composite, common); +} + +extern const struct clk_ops owl_comp_div_ops; +extern const struct clk_ops owl_comp_fact_ops; +extern const struct clk_ops owl_comp_pass_ops; + +#endif /* _OWL_COMPOSITE_H_ */